AD9878BST | |
|---|---|
| Manufacturer Part Number | AD9878BST |
| Description | IC FRONT-END MIXED-SGNL 100-LQFP |
| Manufacturer | Analog Devices Inc |
| AD9878BST datasheets |
|
Availability: In stock
International delivery:
Warranty: 60 days
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Specifications of AD9878BST | |||
|---|---|---|---|
| Rohs Status | RoHS non-compliant | Number Of Bits | 12 |
| Number Of Channels | 4 | Power (watts) | 673mW |
| Voltage - Supply, Analog | 3.3V | Voltage - Supply, Digital | 3.3V |
| Package / Case | 100-LQFP | ||
PrevNext
ADC VOLTAGE REFERENCES
The AD9878 has three independent internal references for its
10-bit and 12-bit ADCs. Both 12-bit and 10-bit ADCs are
designed for 2 V p-p input voltages and have their own internal
reference. Figure 29 shows the proper connections of the REFT
and REFB reference pins. External references might be necessary
for systems that require high accuracy gain matching between
ADCs, or for improvements in temperature drift and noise
characteristics. External references REFT and REFB must be
centered at AVDD/2, with offset voltages as specified by the
following equations:
−
−
+
REFT
10
,
12
:
AVDD
2
0
5 .
V
−
−
−
REFT
10
,
12
:
AVDD
2
0
5 .
V
A differential level of 1 V between the reference pins results in a
2 V p-p ADC input level AIN. Internal reference sources can be
powered down when external references are used (Address 0x02).
VIDEO INPUT
For sampling video-type waveforms, such as NTSC and PAL
signals, the video input channel provides black-level clamping.
Figure 37 shows the circuit configuration for using the video
channel input (Pin 98). An external blocking capacitor is used
with the on-chip video clamp circuit to level-shift the input signal
to a desired reference point. The clamp circuit automatically
senses the most negative portion of the input signal and adjusts
the voltage across the input capacitor. This forces the black level
of the input signal to be equal to the value programmed in the
clamp level register (Register Address 0x07).
By default, the video input is disabled and disconnected from
both ADCs. By setting Register 0x07, Bit 7 = 1, the video input
is enabled and connected to the ADC input as determined by
the state of Reg 0x03, Bit 6 ( 0= ADC12A connected, 1 =
ADC12B connected.)
CLAMP LEVEL + FS/2
CLAMP LEVEL
AD9878
12
ADC
–
+
CLAMP
LEVEL
LPF
Figure 37. Video Clamp Circuit Input
Rev. A | Page 29 of 36
AD9878
VIDEO INPUT
BUFFER
0.1µF
2mA
DAC
OFFSET
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