AD9878BST

Manufacturer Part NumberAD9878BST
DescriptionIC FRONT-END MIXED-SGNL 100-LQFP
ManufacturerAnalog Devices Inc
AD9878BST datasheets

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Specifications of AD9878BST

Rohs StatusRoHS non-compliantNumber Of Bits12
Number Of Channels4Power (watts)673mW
Voltage - Supply, Analog3.3VVoltage - Supply, Digital3.3V
Package / Case100-LQFP  
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AD9878
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
99
100
DRGND
1
DRVDD
2
(MSB) IF12(11)
3
IF12(10)
4
IF12(9)
5
IF12(8)
6
IF12(7)
7
IF12(6)
8
IF12(5)
9
IF12(4)
10
IF12(3)
11
IF12(2)
12
IF12(1)
13
IF12(0)
14
(MSB) IF10(4)
15
IF10(3)
16
IF10(2)
17
IF10(1)
18
IF10(0)
19
RxSYNC
20
DRGND
21
DRVDD
22
MCLK
23
DVDD
24
DGND
25
26
27
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
1, 21, 70
DRGND
2, 22, 71
DRVDD
3
(MSB) IF12(11)
4 to 14
IF12[10:0]
15
(MSB) IF10(4)
16 to 19
IF10[3:0]
20
RxSYNC
23
MCLK
24, 33, 35, 39
DVDD
25, 34, 36, 40
DGND
26
TxSYNC
27
(MSB) TxIQ(5)
28 to 32
TxIQ[4:0]
37
PROFILE
38
RESET
41
SCLK
42
CS
43
SDIO
98
97
96
95
94
93
92
91
90
89
88
87
86
85
AD9878
TOP VIEW
(Not to Scale)
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29
30
31
32
33
34
35
36
37
38
39
40
41
Figure 2. Pin Configuration
Descriptions
Pin Driver Digital Ground
Pin Driver Digital 3.3 V Supply
12-Bit ADC Digital Ouput
12-Bit ADC Digital Ouput
10-Bit ADC Digital Ouput
10-Bit ADC Digital Ouput
Sync Output, 10-Bit and 12-Bit ADCs
Master Clock Output
Digital 3.3 V Supply
Digital Ground
Sync Input for Transmit Port
Digital Input for Transmit Port
Digital Input for Transmit Port
Profile Selection Input
Chip Reset Input
SPORT Clock
SPORT Chip Select
SPORT Data I/O
Rev. A | Page 8 of 36
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83
82
81
80
79
78
77
76
REFT10
75
REFB10
74
AGND10
73
AVDD10
72
DRVDD
71
DRGND
70
REFCLK
69
SIGDELT
68
FLAG1
67
FLAG2
66
CA_EN
65
CA_DATA
64
CA_CLK
63
DVDDOSC
62
OSCIN
61
XTAL
60
DGNDOSC
59
AGNDPLL
58
PLLFILT
57
AVDDPLL
56
DVDDPLL
55
DGNDPLL
54
AVDDTx
53
Tx+
52
Tx–
51
42
43
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