AD73311LAR Analog Devices Inc, AD73311LAR Datasheet
AD73311LAR
Specifications of AD73311LAR
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AD73311LAR Summary of contents
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AVDD1 ANALOG VINP LOOPBACK/ SINGLE-ENDED ENABLE VINN VOUTP CONTINUOUS +6/–15dB PGA LOW-PASS FILTER VOUTN REFCAP REFERENCE REFOUT AGND1 General Purpose Analog Front End GENERAL DESCRIPTION The AD73311L is a complete front-end processor for general purpose applications including speech and ...
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AD73311L–SPECIFICATIONS Parameter REFERENCE REFCAP Absolute Voltage, V REFCAP REFCAP TC REFOUT Typical Output Impedance Absolute Voltage, V REFOUT Minimum Load Resistance Maximum Load Capacitance ADC SPECIFICATIONS 2, 3 Maximum Input Range at VIN Nominal Reference Level at VIN (0 dBm0) ...
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Parameter DAC SPECIFICATIONS (Continued) Power Supply Rejection 4, 5 Group Delay 2, 7 Output DC Offset 2, 8 Minimum Load Resistance Single-Ended Differential 2, 8 Maximum Load Capacitance Single-Ended Differential FREQUENCY RESPONSE 9 (ADC AND DAC) ...
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AD73311L Parameter Condition V REFCAP V REFOUT ADC Maximum Input Range at V Nominal Reference Level DAC Maximum Voltage Output Swing Single-Ended Differential Nominal Voltage Output Swing Single-Ended Differential Output Bias Voltage TIMING CHARACTERISTICS Limit at Parameter T = –40 ...
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SE (I) THREE- STATE SCLK (O) SDIFS (I) SDI (I) t THREE- 9 STATE SDOFS (O) THREE- STATE SDO ( –10 –85 –75 –65 –55 –45 –35 –25 V – dBm0 ...
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... AGND2 ORDERING GUIDE Temperature Model Range AD73311LAR –40°C to +105°C AD73311LARS –40°C to +105°C AD73311LARU –40°C to +105°C EVAL-AD73311LEB Evaluation Board NOTES 0.3' Small Outline IC (SOIC Shrink Small Outline Package (SSOP Thin Small Shrink Outline Package (TSSOP). 2 The AD73311L evaluation board features a cascade of two codecs interfaced to an ADSP-2185L DSP ...
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Pin Number Mnemonic Function 1 VOUTP Analog Output from the Positive Terminal of the Output Channel. 2 VOUTN Analog Output from the Negative Terminal of the Output Channel. 3 AVDD1 Analog Power Supply Connection for the Output Driver. 4 AGND1 ...
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AD73311L TERMINOLOGY Absolute Gain Absolute gain is a measure of converter gain for a known signal. Absolute gain is measured (differentially) with a 1 kHz sine wave at 0 dBm0 for the DAC and with a 1 kHz sine wave ...
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FUNCTIONAL DESCRIPTION Encoder Channel The encoder channel consists of an input configuration block, a switched capacitor PGA and a sigma-delta analog-to-digital converter (ADC). An on-board digital filter, which forms part of the sigma-delta ADC, also performs critical system-level filtering. Due ...
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AD73311L F = 4kHz B SIGNAL TRANSFER FUNCTION NOISE TRANSFER FUNCTION F = 4kHz 4kHz FS = DMCLK/256 B INTER F = 4kHz FS = 8kHz FS = DMCLK/256 B FINAL INTER Decimation Filter The digital filter ...
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The output of the interpolation filter is fed to the DAC’s digital sigma-delta modulator, which converts the 16-bit data to 1-bit samples at a rate of DMCLK/8. The modulator noise-shapes the signal so that errors inherent to the process are ...
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AD73311L MCLK (EXTERNAL RESET SDIFS SDI 8 CONTROL CONTROL REGISTER A REGISTER B SPORT Register Maps There are two register banks for the AD73311L: the control register bank and the data register bank. The control register bank consists ...
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Table VIII. DAC Timing Control DA4 DA3 DA2 DA1 DA0 — — — — — ...
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AD73311L CONTROL REGISTER A 7 RESET Bit CONTROL REGISTER B 7 CEE Bit CONTROL REGISTER C 7 – Bit ...
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CONTROL REGISTER D 7 MUTE Bit CONTROL REGISTER E 7 – Bit CONTROL REGISTER F 7 ALB Bit ...
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AD73311L Operating Modes There are five operating modes available on the AD73311L. Two of these—Digital Loop-Back and Sport Loop-Back—are provided as diagnostic modes with the other three, Program, Data and Mixed Program/Data, being available for general purpose use. The device ...
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SE SCLK SDOFS SDO SAMPLE WORD (DEVICE 1) SDIFS SDI DATA (CONTROL) WORD (DEVICE 1) SE SCLK SDOFS(2) SDO(2) SAMPLE WORD (DEVICE 2) SDOFS(1) SDIFS(2) SDO(1) SAMPLE WORD (DEVICE 1) SDI(2) SDIFS(1) SDI(1) DATA (CONTROL) WORD (DEVICE 2) SAMPLE WORD ...
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AD73311L ANALOG LOOP-BACK SELECT VINP VINN VOUTP CONTINUOUS +6/–15dB LOW-PASS PGA VOUTN REFOUT REFERENCE REFCAP INTERFACING The AD73311L can be interfaced to most modern DSP engines using conventional serial port connections and an extra enable control line. Both serial input ...
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When using the indirectly coupled frame sync configuration in cascaded operation it is necessary to be aware of the restrictions in sending data to all devices in the cascade. Effectively the time allowed is given by the sampling interval (256/DMCLK) ...
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AD73311L The AD73311L also features direct sampling at the lower rate of 8 kHz. This is achieved by the use of extended decimation registers within the decimator block, which allows for the increased word growth associated with the higher effective ...
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FREQUENCY – the AD73311L can be operated at 8 kHz (see Figure 21 kHz sampling rates, which make it particularly ...
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AD73311L 20 0 –20 –40 –60 –80 –100 FREQUENCY – the DAC section, increasing the sampling rate by interpola- tion creates images of the original waveform at intervals of the original sampling frequency. ...
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The dc biasing of the analog input signal is accomplished with an on-chip voltage reference. If the input signal is not biased at the internal reference level (via REFOUT), it must be ac-coupled should be 0.1 µF or larger. with ...
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AD73311L VINP C2 VINN ELECTRET MICROPHONE VOUTP +6/–15dB VOUTN REFOUT REFCAP C REFCAP Analog Output The AD73311L’s differential analog output (VOUT) is pro- duced by an on-chip differential amplifier. The ...
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SDIFS TFS DT SCLK SCLK ADSP-218x DR DSP RFS SDOFS RESET FL0 FL1 FSX DT CLKX TMS320C5x CLKR DSP DR FSR SDOFS RESET XF Cascade Operation Where it is required to configure a cascade eight devices, it ...
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AD73311L DIGITAL GROUND ANALOG GROUND Avoid running digital lines under the device for they will couple noise onto the die. The analog ground plane should be allowed to run under the AD73311L to avoid noise coupling. The power supply lines ...
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Interrupts The AD73311L transfers and receives information over the serial connection from the DSP’s SPORT. This occurs following reset—during the initialization phase—and in both Data-Mode and Mixed-Mode. Each transfer of data to or from the DSP can cause a SPORT ...
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AD73311L In the main body of the program, the code loops waiting for the initialization sequence to be completed. check_init: ax0 = dm (stat_flag pass ax0 jump check_init; If the AD73311L is used in a cascade ...
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Configuring an AD73311L to Operate in Data Mode This section describes the typical sequence of control words that are required to be sent to an AD73311L to set it up for data mode operation. In this sequence, Registers B, C ...
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AD73311L Configuring an AD73311L to Operate in Mixed Mode This section describes a typical sequence of control words that would be sent to an AD73311L to configure it for operation in mixed mode not intended ...
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Step DSP Tx 1 DON’T CARE xxxxxxxxxxxxxxxx 2 CRA-CH1 1000101011111001 3 DON’T CARE xxxxxxxxxxxxxxxx 4 DON’T CARE xxxxxxxxxxxxxxxx 5 CRB-CH1 1000100100001001 6 DON’T CARE xxxxxxxxxxxxxxxx 7 DON’T CARE xxxxxxxxxxxxxxxx 8 CRC-CH1 1000101011111001 9 DAC WORD 0111111111111111 10 DAC WORD 1000000000000000 ...
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AD73311L Configuring a Cascade of Two AD73311Ls to Operate in 1 Data Mode This section describes the typical sequence of control words that are required to be sent to a cascade of two AD73311Ls to set them up for data ...
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DSP Step Tx 1 CRB-CH2 1000100100001011 2 CRB-CH1 1000000100001011 3 CRC-CH2 1000101011111001 4 CRC-CH2 1000101011111001 5 CRC-CH1 1000001011111001 6 CRA-CH2 1000100000010001 7 CRA-CH2 1000100000010001 8 CRA-CH1 1000000000010001 9 CRB-CH2 0111111111111111 10 DAC WORD CH 2 0111111111111111 11 DAC WORD CH ...
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AD73311L Configuring a cascade of two AD73311Ls to Operate in Mixed Mode This section describes a typical sequence of control words that would be sent to a cascade of two AD73311Ls to configure them for operation in mixed mode. It ...
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DSP Step Tx DON’T CARE 1 xxxxxxxxxxxxxxxx DON’T CARE 2 xxxxxxxxxxxxxxxx CRA-CH2 3 1000101011111001 CRA-CH1 4 1000000000010011 DON’T CARE 5 xxxxxxxxxxxxxxxx DON’T CARE 6 xxxxxxxxxxxxxxxx DON’T CARE 7 xxxxxxxxxxxxxxxx CRB-CH2 8 1000100100001011 CRB-CH1 9 1000000100001011 DON’T CARE 10 xxxxxxxxxxxxxxxx DON’T ...
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AD73311L APPENDIX E DAC Timing Control Example The AD73311’s DAC is loaded from the DAC register contents just before the ADC register contents are loaded to the serial register (SDOFS going high). This default DAC load position can be advanced ...