AD9875BST Analog Devices Inc, AD9875BST Datasheet
AD9875BST
Specifications of AD9875BST
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AD9875BST Summary of contents
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A FEATURES Low Cost 3.3 V-CMOS Mixed-Signal Front End (MxFE™) Converter for Broadband Modems 10-/12-Bit D/A Converter (TxDAC+ 64/32 MSPS Input Word Rate 2 /4 Interpolating LPF or BPF Transmit Filter 128 MSPS DAC Output Update Rate Wide (26 ...
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AD9875–SPECIFICATIONS Parameter OSC IN CHARACTERISTICS Frequency Range Duty Cycle Input Capacitance Input Impedance CLOCK OUTPUT CHARACTERISTICS CLKA Jitter (f Derived from PLL) CLKA CLKA Duty Cycle CLKB Jitter (f Derived from PLL) CLKB CLKB Duty Cycle Tx CHARACTERISTICS Tx Path ...
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Parameter Rx PATH GAIN/OFFSET Minimum Programmable Gain Maximum Programmable Gain (12 MHz Filter) (26 MHz Filter) Gain Step Size Gain Step Accuracy Gain Range Error Offset Error, PGA Gain = 0 dB (AD9875) Absolute Gain Error, PGA Gain = 0 ...
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AD9875 –SPECIFICATIONS Parameter Tx PATH INTERFACE Maximum Input Nibble Rate, 2× Interpolation Tx-Set Up Time ( Tx-Hold Time ( PATH INTERFACE Maximum Output Nibble Rate Rx-DataValid Time ( Rx-Data Hold Time (t ) ...
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... Temperature Range AD9875BST –40°C to +85°C AD9875-EB –40°C to +85°C AD9875BSTRL –40°C to +85°C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9875 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges ...
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AD9875 Pin Name 1 OSCIN SENABLE 2 3 SCLK 4 SDATA 5, 38, 47 AVDD 6, 9, 39, 42, 43, 46 AVSS 7 Tx+ 8 Tx– 10 FSADJ 11 REFIO 12 PWR DN 13 DVSS 14 DVDD ...
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DEFINITIONS OF SPECIFICATIONS CLOCK JITTER The clock jitter is a measure of the intrinsic jitter of the PLL generated clocks measure of the jitter from one rising and of the clock with respect to another edge of ...
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AD9875 –Typical Tx Digital Filter Performance Characteristics 10 0 INTERPOLATION –10 FILTER –20 –30 –40 INCLUDING SIN(X)/X –50 –60 –70 –80 –90 –100 0.0 0.1 0.2 0.3 0.4 0.5 0.6 NORMALIZED – TPC 1. 4 Low-Pass Interpolation Filter ...
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Typical AC Characteristics Curves for TxDAC 10 0 –10 –20 –30 –40 –50 –60 –70 –80 – FREQUENCY – MHz TPC 7. Single Tone Spectral Plot @ MHz, 4 ...
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AD9875 Typical AC Characteristics Curves for TxDAC 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 – FREQUENCY OFFSET – kHz TPC 13. Phase Noise Plot @ ...
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Typical AC Characterization Curves for Rx Path 112 128 TPC 17. Rx vs. Tuning Target, f ADC Wideband Rx LPF = 1 0.60 0.40 0.20 0.00 ...
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AD9875 Typical AC Characterization Curves for Rx Path LOG MAG 5dB/REF 0dB 0 1MHz 10MHz TPC 21. Rx LPF Frequency Response, Low f Tuning Targets LOG MAG 5dB/REF 0dB 1MHz 10MHz TPC 22. Rx LPF Frequency Response, High f Tuning ...
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Typical AC Characterization Curves for Rx Path LOG DELAY 5dB/REF –2dB 33.5MHz 1MHz 10MHz TPC 27. Rx LPF Frequency Response, High Tuning Targets LOG MAG 5dB/REF 0dB 78.8MHz 0 10kHz 100kHz TPC 28. Rx HPF Frequency Response, ...
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AD9875 Typical AC Characterization Curves for Rx Path 10.0 9.5 f OSCIN 9.0 8.5 f PLLB/2 8.0 7.5 7 – MHz S TPC 33. Rx Path ENOB vs. f ADC ...
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TRANSMIT PATH The AD9875 transmit path consists of a Digital Interface Port, a Programmable Interpolation Filter, and a Transmit DAC. All clock signals required by these blocks are generated from the f signal by the PLL-A clock generator. The block ...
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AD9875 typically drive a resistive load which will convert the output currents to a voltage. The Tx+ and Tx– output currents are inherently ground seeking and should each be connected to matching resistors that are tied directly to ...
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The digital data outputs of the ADC are represented in two’s complement format. They saturate to full-scale or zero when the input signal exceeds the input voltage range. The two’s complement data format is shown below: 011 . . 11: ...
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AD9875 AGC TIMING CONSIDERATIONS When implementing the AGC timing loop it is important to consider the delay and settling time of the Rx path in response to a change in gain. Figure 4 shows the delay the receive signal experiences ...
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For the AD9875, the most significant nibble defaults to six bits and the least significant nibble defaults to four bits. This can be changed so that the least significant nibble and most significant nibble have five bits each. This is ...
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AD9875 increment the address for each successive byte required for the multibyte communication cycle. Figures 10a and 10b show how the serial port words are built for each of these modes. INSTRUCTION CYCLE DATA TRANSFER CYCLE SENABLE SCLK R/W I6 ...
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REGISTER PROGRAMMING DEFINITIONS REGISTER 0—RESET/SPI Configuration Bit 5: Software Reset Setting this bit high resets the chip. The PLLs will relock to the input clock and all registers (except Register 0 × 0, Bit 6) revert to their default values. ...
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AD9875 Bit 2: Wideband Rx LPF This bit selects the nominal cutoff frequency of the 4-pole LPF. Setting this bit high selects a nominal cutoff frequency of 28.8 MHz. When the wideband filter is selected, the Rx path gain is ...
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Bit 3: Power-Down Interpolator at TxQUIET Pin Low Setting Bit 3 high enables the TxQUIET pin to shut off the DAC output. If the bit is set to one, then pulling the TxQUIET pin low will power down the interpolator ...
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AD9875 The AVDD and DVDD power planes may be fed from the same low noise voltage source; however, they should be decoupled from each other to prevent the noise generated in the DVDD portion of the MxFE from corrupting the ...
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SEATING 0.05 PLANE ROTATED 90 CCW REV. A OUTLINE DIMENSIONS 48-Lead Plastic Quad Flatpack [LQFP] (ST-48) Dimensions shown in millimeters 1.60 MAX PIN 1 INDICATOR 0.75 0.60 0.45 1 SEATING PLANE 0.20 0.09 VIEW A 7 ...
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AD9875 Revision History Location 8/02—Data Sheet changed from REV REV. A. Changes to Table ...
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