AD9876ABSTRL Analog Devices Inc, AD9876ABSTRL Datasheet
AD9876ABSTRL
Specifications of AD9876ABSTRL
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AD9876ABSTRL Summary of contents
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A FEATURES Low Cost 3.3 V CMOS Mixed-Signal Front End (MxFE™) Converter for Broadband Modems 10-/12-Bit D/A Converter (TxDAC+ 64/32 MSPS Input Word Rate 2 /4 Interpolating LPF or BPF Transmit Filter 128 MSPS DAC Output Update Rate Wide ...
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AD9876–SPECIFICATIONS Parameter OSCIN CHARACTERISTICS Frequency Range Duty Cycle Input Capacitance Input Impedance CLOCK OUTPUT CHARACTERISTICS CLK A Jitter (f Derived from PLL) CLKA CLK A Duty Cycle CLK B Jitter (f Derived from PLL) CLKB CLK B Duty Cycle Tx ...
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Parameter Rx PATH GAIN/OFFSET Minimum Programmable Gain Maximum Programmable Gain (12 MHz Filter) Maximum Programmable Gain (26 MHz Filter) Gain Step Size Gain Step Accuracy Gain Range Error Offset Error, PGA Gain = 0 dB Absolute Gain Error Rx PATH ...
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AD9876 Parameter Tx PATH INTERFACE Maximum Input Nibble Rate, 2× Interpolation Tx Setup Time ( Hold Time ( PATH INTERFACE Maximum Output Nibble Rate Rx Data Valid Time ( Data Hold ...
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ABSOLUTE MAXIMUM RATINGS* Power Supply ( 3 Digital ...
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AD9876 Pin No. Mnemonic 1 OSCIN SENABLE 2 3 SCLK 4 SDATA 5, 38, 47 AVDD 6, 9, 39, 42, 43, 46 AVSS 7 Tx+ 8 Tx– 10 FSADJ 11 REFIO 12 PWR DN 13 DVSS 14 DVDD 15 FB ...
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DEFINITIONS OF SPECIFICATIONS CLOCK JITTER The clock jitter is a measure of the intrinsic jitter of the PLL generated clocks measure of the jitter from one rising and of the clock with respect to another edge of ...
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AD9876 –Typical Tx Digital Filter Performance Characteristics 10 0 INTERPOLATION –10 FILTER –20 –30 –40 INCLUDING SIN(X)/X –50 –60 –70 –80 –90 –100 0.0 0.1 0.2 0.3 0.4 0.5 0.6 NORMALIZED – TPC 1. 4 Low-Pass Interpolation Filter ...
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Typical AC Characteristics Curves for TxDAC –10 –20 –30 –40 –50 –60 –70 –80 – FREQUENCY – MHz TPC 7. Single-Tone Spectral Plot @ MHz, 4 LPF ...
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AD9876 Typical AC Characteristics Curves for TxDAC 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 – FREQUENCY OFFSET – kHz TPC 13. Phase Noise Plot @ ...
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Typical Tx Digital Filter Performance Characteristics 112 128 TPC 17. Rx vs. Tuning Target, f LPF with Wideband Rx LPF = 1 0.60 0.40 0.20 0.00 ...
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AD9876 Typical AC Characterization Curves for Rx Path LOG MAG 5dB/REF – 0dB 0 1MHz 10MHz TPC 21. Rx LPF Frequency Response, Low f Nominal Tuning Targets LOG MAG 5dB/REF 0dB 1MHz 10MHz TPC 22. Rx LPF Frequency Response, High ...
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Typical AC Characterization Curves for Rx Path LOG DELAY 5dB/REF –2dB 33.5MHz 1MHz 10MHz TPC 27. Rx LPF Frequency Response, High and 0 96 Tuning Targets LOG MAG 5dB/REF 0dB 78.8MHz 0 COR AVG 16 10kHz 100kHz ...
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AD9876 Typical AC Characterization Curves for Rx Path 11.0 10.5 f OSCIN 10.0 9.5 9.0 f PLLB/2 8.5 8.0 7.5 7 – MHz S TPC 33. Rx Path ENOB vs. f ADC 11.0 10.5 ...
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TRANSMIT PATH The AD9876 transmit path consists of a digital interface port, a programmable interpolation filter, and a transmit DAC. All clock signals required by these blocks are generated from the f signal by the PLL-A clock generator. The block ...
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AD9876 D/A CONVERTER The AD9876 DAC provides differential output current on the Tx+ and Tx– pins. The value of the output currents are comple- mentary, meaning that they will always sum to I current of the DAC. For example, when ...
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AINP AINN SHA GAIN A/D D/A A/D CORRECTION LOGIC Figure 2. ADC Theory of Operation The digital data outputs of the ADC are represented in two’s complement format. They saturate to full scale or zero when the input signal exceeds ...
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AD9876 AGC TIMING CONSIDERATIONS When implementing the AGC timing loop important to consider the delay and settling time of the Rx path in response to a change in gain. Figure 4 shows the delay the receive signal experiences ...
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Inverting CLK-A would affect the Tx sampling edge as well as the Rx sampling edge. The first nibble of each word can be read in as the least significant nibble by setting the Rx LS Nibble First Bit (Register ...
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AD9876 the first address to be accessed. The AD9876 will automatically increment the address for each successive byte required for the multibyte communication cycle. Figures 10a and 10b show how the serial port words are built for each of these ...
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REGISTER PROGRAMMING DEFINITIONS REGISTER 0 – RESET/SPI CONFIGURATION Bit 5: Software Reset Setting this bit high resets the chip. The PLLs will relock to the input clock and all registers (except Register 0 × 0, Bit 6) revert to their ...
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AD9876 Bit 2: Wideband Rx LPF This bit selects the nominal cutoff frequency of the 4-pole LPF. Setting this bit high selects a nominal cutoff frequency of 28.8 MHz. When the wideband filter is selected, the Rx path gain is ...
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Bit 4 to Bit 7: Interpolation Filter Select Bits define the interpolation filter characteristics and interpolation rate. Bits 7:4; 0 × 2; Interpolation Bypass 0 × 0; see TPC 1. 4× Interpolation, LPF 0 × 1; see ...
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AD9876 on the MxFE side of the ferrite as well as a low ESR, ESL decoupling capacitors on each supply pin (i.e., the AD9876 requires five power supply decoupling caps, one each on Pins 5, 38, 47, 14, and 35). ...