CS5526-BSZ Cirrus Logic Inc, CS5526-BSZ Datasheet
CS5526-BSZ
Specifications of CS5526-BSZ
Available stocks
Related parts for CS5526-BSZ
CS5526-BSZ Summary of contents
Page 1
... Latch A2 A3 CPD http://www.cirrus.com General Description The 16-bit CS5525 and the 20-bit CS5526 are highly in- tegrated instrumentation amplifier, a PGA (programmable gain amplifier), eight digital filters, and self and system cali- bration circuitry. The converters are designed to provide their own nega- ...
Page 2
... CS5526 2.5 V 1.0 µV 2.0 µV 4.0 µV 1.5 µV 3.0 µV 2.0 µV 5.0 µV 10 µV 4.0 µV 10 µV 15 µV 15 µV 45 µV 85 µV 72 µV 190 µV 350 µV 340 µV 900 µV 2 ...
Page 3
... The maximum full-scale signal can be limited by saturation of circuitry within the internal signal path. 11. All outputs unloaded. All input CMOS levels. DS202F5 (Continued) Bipolar/Unipolar Mode -0.150 (Note 5) Bipolar/Unipolar Mode (Note 9) Bipolar/Unipolar Mode (Note 10 NBV (Note 11) CS5525 CS5526 Min Typ Max Unit - 0.950 V NBV - VA+ V 1.85 - 2.65 V 0.0 ...
Page 4
... VA ±5%; VD+ = 3.0 V ±10%; GND = 0; A Symbol V IH XIN SCLK (VD XIN SCLK -400 µA out CPD -4.0 mA out SDO -5.0 mA out 400 µA out CPD out SDO 5.0 mA out out CS5525 CS5526 Min Typ Max Unit 0.6 VD 3 0.8 V 0 0.6 V (VA (VD (VD+) - 1.0 - ...
Page 5
... Positive Digital VD+ Positive Analog VA+ Negative Potential NBV (Note 16 and 17 OUT (Note 18) PDN VREF pins V INR AIN Pins V INA V IND stg CS5525 CS5526 Ratio Unit XIN/2 Hz 1/f s out Min Typ Max Unit 2.7 5.0 5.25 V 4.75 5.0 5.25 V 1.0 2.5 3.0 V -1.8 -2 ...
Page 6
... Any Digital Output (Note 20) t fall SCLK Any Digital Output (Note 21) t ost t por SCLK t 0 (Note 22) Pulse Width High t 1 Pulse Width Low CS5525 CS5526 Min Typ Max Unit 30 32.768 36 kHz 30 32.768 100 1.0 µ 100 µ 1.0 µ 100 µ ...
Page 7
... Continuous Running SCLK Timing (Not to Scale DS202F5 SDI Write Timing (Not to Scale SDO Read Timing (Not to Scale) CS5525 CS5526 ...
Page 8
... DETAILED DESCRIPTION The CS5525 and CS5526 are 16-bit and 20-bit pin compatible converters which include a chopper- stabilized instrumentation amplifier input, and an on-chip programmable gain amplifier. They are both optimized for measuring low-level unipolar or bipolar signals in process control and medical ap- plications. The CS5525/26 also include a fourth order delta- ...
Page 9
... V (NBV = 0V). Figure 2. Charge Pump Drive Circuit for VD Figure 4. CS5525/26 Configured for ground-referenced Unipolar Signals. DS202F5 CS5525 CS5526 The CS5525/26 are optimized for the measurement of thermocouple outputs, but they are also well suited for the measurement of ratiometric bridge transducer outputs ...
Page 10
... CS5525 CS5526 Command Operation The CS5525/26 include a microcontroller with five registers used to control the converter. Each regis- ter is 24-bits in length except the 8-bit command register (command, configuration, offset, gain, and conversion data). After a system initialization or re- ...
Page 11
... Read from selected register. 000 Offset Register 001 Gain Register 010 Configuration Register 011 Conversion Data Register (read only) 100 Set-up Registers (Offset, Gain, Configuration) 101 Reserved 110 Reserved 111 Reserved 0 Run 1 Power Save Table 1. Command Set CS5525 CS5526 D0 PS/R FUNCTION 11 ...
Page 12
... Offset -- Self-Calibration 010 Gain -- Self-Calibration 011 Offset Self-Calibration followed by Gain Self-Calibration 100 Not used. 101 Offset -- System Calibration 110 Gain -- System Calibration 111 Not Used. Table 2. Configuration Register CS5525 CS5526 D16 D15 D14 D13 LPM WR2 WR1 WR0 PSS DF CC2 ...
Page 13
... clock c ycles for each convers ion except the first conv ersion w hich w ill take clock c ycles DS202F5 ( t giste rite C ycle ata ( for S et gisters ) Read C ycle tin nversion R ead ( Figure 6. Command and Data Word Timing. CS5525 CS5526 LSB LSB ata ...
Page 14
... If the sig ula to r Figure 7. Block Diagram of Analog Signal Path CS5525 CS5526 ABS(VIN + VOS 2.8 V VIN = (AIN+) - (AIN ita l F ilter D iffere ntial rder d e lta - DS202F5 ...
Page 15
... For physical input capacitance see ‘Input Capacitance’ spec- ification under ‘Analog Characteristics’ on page 3. ≤ Figure 8. Input models for AIN+ and AIN- pins Figure 9. Input model for VREF+ and VREF- pins. CS5525 CS5526 ∆-Σ Nominal (1) ∆-Σ Differential Input Max. Input ± 0.5 V ± 0.75 V ± 1.1 V ± ...
Page 16
... The converters can typically trim ±50 percent of the input span. The gain register spans from decimal equivalent meaning of the gain register where the binary numbers have a value of either zero or one (b 4 Table for details. CS5525 CS5526 -23 N ∑ – 2 – – N … ...
Page 17
... VREF- pin as shown in Figure 11. For self-calibration of gain, the differential inputs of the modulator are connected to VREF+ and OPEN AIN+ AIN- Figure 10. Self Calibration of Offset (Low Ranges). AIN+ AIN- VREF- Figure 11. Self Calibration of Offset (High Ranges). CS5525 CS5526 LSB -21 -22 -23 - ...
Page 18
... Connections + Figure 14. System Calibration of Offset (High Ranges). External Connections Full Scale + - Figure 15. System Calibration of Gain (Low Ranges) External Connections + Full Scale - + CM - Figure 16. System Calibration of Gain (High Ranges). CS5525 CS5526 + AIN+ X20 - AIN- + AIN+ X20 - AIN- + AIN+ X20 - AIN- + AIN+ X20 - AIN- ...
Page 19
... System calibration can be limited by signal head- room in the analog signal path inside the chip as discussed under the Analog Input section of this data sheet. System calibration can also be limited by the intrinsic gain errors of the instrumentation amplifier and the modulator. For gain calibrations CS5525 CS5526 19 ...
Page 20
... Performing Conversions (With PF bit = 0) Setting the SC (Single Conversion) bit of the com- mand word to a logic 1 with the CB bit = 1, all other command bits = 0, the CS5525/CS5526 will per- form one conversion. At the completion of the con- version the DF (Done Flag) bit of the configuration register will be set to a logic 1. The user can read the configuration register to determine if the DF bit is set ...
Page 21
... DS202F5 CS5525 CS5526 Output Word Rate Selection The WR2-WR0 bits of the configuration register set the output conversion word rate of the convert- ers as shown in Table 2. The word rates indicated in the table assume a master clock of 32 ...
Page 22
... For the CS5525 the last byte is composed of bits D7-D4, which are always logic 1; D3-D2, which are always logic 0; and bits D1-D0 which are the two flag bits. For the CS5526 the last byte in- cludes data bits D7-D4, D3-D2 which are always logic 0 and the two flag bits. ...
Page 23
... The par- ticular power save mode entered depends on state of bit D4 (the Power Save Select bit) in the configura- tion register logic 0, the converters enters the standby mode reducing the power consumption to DS202F5 CS5526 20-Bit Output Coding Two's Unipolar Input Offset Complement Voltage ...
Page 24
... VREF- VOLTAGE REFERENCE INPUT 3 18 AIN+ CS CHIP SELECT 4 17 AIN- SDI SERIAL DATA INPUT 5 16 NBV A3 LOGIC OUTPUT LOGIC OUTPUT SDO SERIAL DATA OUTPUT 8 13 CPD VD+ POSITIVE DIGITAL POWER 9 12 XIN DGND DIGITAL GROUND 10 11 XOUT SCLK SERIAL CLOCK INPUT CS5525 CS5526 DS202F5 ...
Page 25
... Square wave output used to provide energy for the charge pump. Power Supply Connections VA+ - Positive Analog Power, Pin 2. Positive analog supply voltage. Nominally +5 V. VD+ - Positive Digital Power, Pin 13. Positive digital supply voltage. Nominally +3 AGND - Analog Ground, Pin 1. Analog Ground. DGND - Digital Ground, Pin 12. Digital Ground. DS202F5 CS5525 CS5526 25 ...
Page 26
... AIN- pin.). When in unipolar mode (U/B bit = 1). Units are in LSBs. Bipolar Offset The deviation of the mid-scale transition(111...111 to 000...000) from the ideal (1/2 LSB below the voltage on the AIN- pin). When in bipolar mode (U/B bit = 0). Units are in LSBs. 26 CS5525 CS5526 DS202F5 ...
Page 27
... CS5525 CS5526 ∝ SIDE VIEW MILLIMETERS MAX 4.57 1.02 0.56 1.65 0.38 26.42 6.60 2.67 8.25 3.81 0° 15° 27 ...
Page 28
... CS5525 CS5526 1 E1 END VIEW L NOTE MILLIMETERS MAX -- 2.13 0.25 1.88 0.38 2,3 7.50 1 8.20 5.60 1 0.69 1.03 8° ...
Page 29
... CS5526-BS CS5526-BSZ (Lead Free) ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number CS5525-AS CS5525-ASZ (Lead Free) CS5526-BP CS5526-BS CS5526-BSZ (Lead Free) * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. DS202F5 Package 20-pin SSOP 20-pin Plastic Dip (0.300”) 20-pin SSOP Peak Reflow Temp MSL Rating* 240 ° ...
Page 30
... Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation. 30 CS5525 CS5526 Changes DS202F5 ...