AD7663ASTZ Analog Devices Inc, AD7663ASTZ Datasheet - Page 4

• Manufacturer Part Number: AD7663ASTZ
• Description: IC ADC 16BIT CMOS 48-LQFP
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7663ASTZ

• Data Interface: Serial, Parallel
• Number Of Bits: 16
• Sampling Rate (per Second): 250k
• Number Of Converters: 1
• Power Dissipation (max): 41mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Resolution (bits): 16bit
• Sampling Rate: 250kSPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 4.75V To 5.25V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7663CBZ - BOARD EVALUATION FOR AD7663
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TIMING SPECIFICATIONS
Parameter
Refer to Figures 17 and 18 (Master Serial Interface Modes)
Refer to Figures 19 and 21 (Slave Serial Interface Modes)
NOTES
1
2
Specifications subject to change without notice.
AD7663
DIVSCLK[1]
DIVSCLK[0]
SYNC to SCLK First Edge Delay Minimum
Internal SCLK Period Minimum
Internal SCLK Period Maximum
Internal SCLK HIGH Minimum
Internal SCLK LOW Minimum
SDOUT Valid Setup Time Minimum
SDOUT Valid Hold Time Minimum
SCLK Last Edge to SYNC Delay Minimum
BUSY HIGH Width Maximum
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
In Serial Master Read during Convert Mode. See Table II for Master Read after Convert Mode.
CS HIGH to SYNC HI-Z
CS HIGH to Internal SCLK HI-Z
CS HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read after Convert
CNVST LOW to SYNC Asserted Delay
SYNC Deasserted to BUSY LOW Delay
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
External SCLK HIGH
External SCLK LOW
(Master Serial Read after Convert)
Figure 1. Load Circuit for Digital Interface Timing
*IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
TO OUTPUT
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD
C
L
OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
PIN
C
60pF*
L
500 A
1.6mA
Table II. Serial Clock Timings in Master Read after Convert
I
I
OH
OL
(continued)
1.4V
t
t
t
t
t
t
t
t
t
18
19
19
20
21
22
23
24
28
1
–4–
t
t
Symbol
t
t
t
t
t
t
t
t
t
t
t
25
26
27
28
29
30
31
32
33
34
35
36
37
0
0
4
25
40
15
9.5
4.5
2
3
2
Figure 2. Voltage Reference Levels for Timing
Min
5
3
5
5
25
10
10
0
1
20
50
70
25
24
22
4
60
2.5
t
L
DELAY
0.8V
of 10 pF; otherwise, the load is 60 pF maximum.
2V
0.8V
Typ
See Table II
1.25
25
1
0
20
100
140
50
49
22
30
140
3.5
2V
1
1
20
200
280
100
99
22
90
300
5.75
Max
10
10
10
16
t
DELAY
2V
0.8V
Unit
ns
ns
ns
ns
ns
ns
ns
ns
µs
REV. B
Unit
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns