CS5508-BSZ Cirrus Logic Inc, CS5508-BSZ Datasheet
CS5508-BSZ
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CS5508-BSZ Summary of contents
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Very Low Power, 16-Bit and 20-Bit A/D Converters Very Low Power, 16-bit & 20-bit A/D Converters Features Very Low Power Consumption l - Single supply +5 V operation: 1 Dual supply ±5 V operation: 3.2 mW Offers superior ...
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ANALOG CHARACTERISTICS 3.3V ± 5%; VREF+ = 2.5V(external); VREF AGND at AIN; Anal og input channel AIN1+; AIN- = AGND; unless otherwise specified.) (Notes 1, 2) Parameter* Specified Temperature Range Accuracy Linearity Error Differential Nonlinearity Full ...
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... VREF = 2.5V CS5506/8; 20-Bit Unit Conversion Factors Symbol out f -3dB t s CS5505/6/7/8 CS5505/6/7 Ω with a source CS5508-S Max Min Typ Max -55 to +125 - 0.0015 0.003 - ±32 - ±8 ± ± ±32 ±16 ±64 ...
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ANALOG CHARACTERISTICS 3.3V ± 5%; VREF+ = 2.5V (external); VREF- = 0V; f 10nF to AGND at AIN; Analog input channel AIN1+; AIN- = AGND; unless otherwise specified.) (Notes 1, 2) Parameter* Specified Temperature Range Analog Input Analog Input Range: ...
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DIGITAL CHARACTERISTICS DGND = 0.) All measurements below are performed under static conditions. (Note 2) Parameter High-Level Input Voltage: All Pins Except XIN and M/SLP Low-Level Input Voltage: All Pins Except XIN and M/SLP M/SLP SLEEP Active Threshold High-Level ...
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SWITCHING CHARACTERISTICS VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; C Parameter Master Clock Frequency: Internal Oscillator: External Clock: Master Clock Duty Cycle Rise Times: Any Digital Input Any Digital Output Fall ...
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SWITCHING CHARACTERISTICS VD+ = 3.3V ± 5%; VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic pF.) (Note 2) Parameter Master Clock Frequency: Internal Oscillator: External Clock: Master Clock ...
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XIN XIN/2 CAL CONV STATE Standby XIN XIN/2 A0 CONV DRDY BP/UP STATE Standby ccw t t scl cal Calibration Figure 1. Calibration Timing (Not to Scale) t hca sac t cpw t t scn ...
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SWITCHING CHARACTERISTICS VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; C Parameter SSC Mode (M/SLP = VD+) Access Time: CS Low to SDATA out (DRDY = low) DRDY falling to MSB (CS ...
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SWITCHING CHARACTERISTICS 5%; VA ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; C Parameter SSC Mode (M/SLP = VD+) Access Time: CS Low to SDATA out (DRDY = low) DRDY falling to ...
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XIN XIN/2 CONV CS STATE Standby Conversion DRDY SCLK(o) Hi-Z SDATA(o) Hi-Z STATE (CONV held high) Conversion1 Figure 3. Timing Relationships; SSC Mode (Not to Scale) DRDY CS t csd2 SDATA(o) Hi-Z SCLK(i) DRDY CS t csd2 SDATA(o) Hi-Z SCLK(i) ...
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RECOMMENDED OPERATING CONDITIONS Parameter DC Power Supplies: Positive Digital (VA+)-(VA-) Positive Analog Negative Analog Analog Reference Voltage (Note 20) (VREF+)-(VREF-) Analog Input Voltage: (Note 21) Unipolar Bipolar Notes: 19. All voltages with r espect to ground. 20. The CS5505/6/7/8 can ...
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GENERAL DESCRIPTION The CS5505/6/7/8 are very low power mono- lith A/D co nverters designed specifically for measurement of dc signals. The CS5505/7 are 16-bit converters (a four channel and a single channel version). The CS5506/8 are 20-bit ...
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The calibration state is entered whenever the CAL and CONV pins are high at the same time. The state of the CAL and CONV pins at ...
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AIN1. The BP/UP pin is not a latched input. The BP/UP pin controls how the output word from the digital filter is processed. In bipolar mode the output word computed by the digital filter is offset by 8000H in the ...
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... VREF - 1.5 LSB -0.5 LSB VREF/2 - 0.5 LSB -VREF + 0.5 LSB +0.5 LSB <(-VREF + 0.5 LSB) <(+0.5 LSB) Table 2. Output Coding CS5505/6/7/8 CS5505/6/7/8 CS5506 and CS5508 (20 Bit) Output Bipolar Input Codes Voltage FFFFF >(VREF - 1.5 LSB) FFFFF VREF - 1.5 LSB FFFFE 80000 -0 ...
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Understanding Converter Calibration Calibration can be performed at any time. A calibration sequence will minimize offset errors and set the gain slope scale factor. The delta- sigma modulator in the converter is a differential modulator. To calibrate out offset error, ...
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Analog Input Impedance Considerations The analog input of the CS5505/6/7/8 can be modeled as illustrated in Figure 8 (the model ig- nores the multiplexer switch resistance). Capacitors (15 pF each) are used to dynamically sample each of the inputs (AIN+ ...
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Digital Filter Characteristics The digital filter in the CS5505/6/7/8 is the com- bination of a comb filter and a low pass filter. The comb filter has zeros in its transfer function which are optimally placed to reject line interfer- ence ...
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If the CS5505/6/7/8 is operated at a clock rate other than 32.768 kHz, the filter characteristics, including the comb filter zeros, will scale with the operating clock frequency. Therefore, opti- mum rejection of line frequency interference will occur with the ...
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Over the military temperature range (- 55 to +125 °C) the on-chip gate oscillator is designed to work only with a 32.768 kHz crys- tal. The chip will ...
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Synchronous External-Clocking Mode The serial port operates in the SEC mode when the M/SLP pin is connected to the DGND pin. SDATA is the output pin for the serial data. When CS goes low after new data becomes available (DRDY ...
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No analog ground pin is re- quired because the inputs for measurement and for the voltage reference are differential and re- quire no ground. In the digital section of the chip the supply current flows into the ...
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Figure 14 illustrates the System Connection Dia- gram for the CS5505/6 using a single +5V supply. Note that all supply pins are bypassed with 0.1 µF capacitors and that the VD+ digital supply is derived from the VA+ supply. Figure ...
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Analog Supply Calibration Control Bipolar/ Unipolar Input Select Analog* Signal Sources Signal Ground *Unused analog inputs should be tied to AIN- + Voltage (1) Reference - Note: (1) To use the internal 2.5 volt reference see Figure 6. (2) ...
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PIN CONNECTIONS* MULTIPLEXER SELECTION INPUT CHIP SELECT CONVERT CALIBRATE CRYSTAL IN CRYSTAL OUT SE RIAL MODE/ SLEEP BIPOLAR/UNIPOLAR DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG RETURN DIFFERENTIAL ANALOG INPUT CHIP SELECT CONVERT CALIBRATE CRYSTAL IN CRYSTAL OUT SERIAL MODE/ ...
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PIN DESCRIPTIONS Pin numbers for four channel devices are in parentheses. Clock Generator XIN; XOUT - Crystal In; Crystal Out, Pins 4 (5) and 5 (6). A gate inside the chip is connected to these pins and can be used ...
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Control Input Pins CAL - Calibrate, Pin 3 (4). When taken high the same time that the CONV pin is taken high the converter will perform a self-calibration which includes calibration of the offset and gain scale factors in the ...
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VD+ - Positive Digital Power, Pin 17 (20). Positive digital supply voltage. Nominally +5 volts or 3.3 volts. DGND - Digital Ground, Pin 16 (19). Digital Ground. Other Connection, Pin 9. Pin should be left floating. SPECIFICATION ...
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... CS5506-BSZ (lead free) CS5507-ASZ (lead free) CS5508-BSZ (lead free) ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number CS5505-ASZ (lead free) CS5506-BSZ (lead free) CS5507-ASZ (lead free) CS5508-BSZ (lead free) * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. 30 Liearity Error Channels 16 Bits 0.0030% 20 Bits ...
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REVISION HISTORY Revision Date F4 MAR 1995 First Final Release F5 AUG 2005 Updated device ordering info. Updated legal notice. Added MSL data.. F7 OCT 2009 Increased minimum Vdiff voltage from 4.5 to 4.75 V. Contacting Cirrus Logic Support For ...
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NOTES - CS5505/6/7/8 DS59F7 ...
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Evaluation Board for CS5505/6/7/8 Series of ADC’s Evaluation Board for CS5505/6/7/8 Series of ADCs Features l Operation with on-board 32.768 kHz crystal or off-board clock source l Jumper selectable: - SSC mode; SEC mode; Sleep l DIP Switch Selectable: - ...
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Introduction The CDB5505/6/7/8 evaluation board provides a quick means of testing the CS5505/6/7/8 series A/D converters. The CS5505/6/7/8 converters require a minimal amount of external circuitry. The evaluation board comes configured with the A/D converter chip operating from a 32.768 ...
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DS59DB4 DS59DB2 CDB5505/6/7/8 CS5505/6/7 ...
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A0 and A1 (see Table 1). Once A0 and A1 are selected, the CONV switch (S2-3) must be switched on (closed) and then open to cause the CONV signal to transition low to high. This latches the A0 and ...
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Figure 3. Top Ground Plane Layer (NOT TO SCALE) DS59DB4 DS59DB2 CDB5505/6/7/8 CS5505/6/7 ...
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Figure 4. Bottom Trace Layer (NOT TO SCALE CDB5505/6/7/8 CS5505/6/7/8 DS59DB4 DS59DB2 ...
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DS59DB4 DS59DB2 Figure 5. Silk Screen Layer (NOT TO SCALE) CDB5505/6/7/8 CS5505/6/7 ...
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REVISION HISTORY Revision Date DB2 MAR 1995 First Release F5 AUG 2005 Updated legal notice. DB4 JUN 2009 Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to ...