IC ADC 20BIT LOW PWR 20-SOIC

CS5508-BSZ

Manufacturer Part NumberCS5508-BSZ
DescriptionIC ADC 20BIT LOW PWR 20-SOIC
ManufacturerCirrus Logic Inc
CS5508-BSZ datasheet
 


Specifications of CS5508-BSZ

Data InterfaceSerialNumber Of Bits20
Sampling Rate (per Second)100Number Of Converters1
Power Dissipation (max)4.5mWVoltage Supply SourceAnalog and Digital, Dual ±
Operating Temperature-40°C ~ 85°CMounting TypeSurface Mount
Package / Case20-SOICResolution (bits)20bit
Sampling Rate100SPSInput Channel TypeDifferential
Supply Current340µADigital Ic Case StyleSOIC
No. Of Pins20Lead Free Status / RoHS StatusLead free / RoHS Compliant
Other names598-1099-5  
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Very Low Power, 16-Bit and 20-Bit A/D Converters
Very Low Power, 16-bit & 20-bit A/D Converters
Features
Very Low Power Consumption
l
- Single supply +5 V operation: 1.7 mW
- Dual supply ±5 V operation: 3.2 mW
Offers superior performance to VFCs and
l
multi-slope integrating ADCs
Differential Inputs
l
- Single-channel (CS5507/8) and Four-channel
(CS5505/6) pseudo-differential versions
Either 5 V or 3.3 V Digital Interface
l
Linearity Error:
l
- ±0.0015% FS (16-bit CS5505/7)
- ±0.0007% FS (20-bit CS5506/8)
Output update rates up to 100 Sps
l
Flexible Serial Port
l
Pin-Selectable Unipolar/Bipolar Ranges
l
I
Cirrus Logic, Inc.
Crystal Semiconductor Products Division
http://www.cirrus.com
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
Description
The CS5505/6/7/8 are a family of low power CMOS A/D
converters which are ideal for measuring low-frequency
signals representing physical, chemical, and biological
processes.
The CS 5507/8 have single-channel differential analog
and reference inputs while the CS5505/6 have four
pseudo-differential analog input channels. The
CS5505/7 have a 16-bit output word. The CS5506/8
have a 20-bit output word.The CS5505/6/7/8 sample
upon command up to 100 Sps.
The on-chip digital filter offers superior line rejection at
50 and 60 Hz when the device is operated from a
32.768 kHz clock (output word rate = 20 Sps).
The CS 5505/6/7/8 include on-chip self-calibration cir-
cuitry which can be initiated at any time or temperature
to ensure minimum offset and full-scale errors.
The CS5505/6/7/8 serial port offers two general-purpose
modes for the direct in terface to shift r egisters or syn-
chronous serial ports of industry-standard
microcontrollers.
ORDERING INFORMATION
See
page
30.
Copyright  Cirrus Logic, Inc. 2009
Copyright © Cirrus Logic, Inc. 1997
(All Rights Reserved)
(All Rights Reserved)
CS5505/6/7/8
µ
OCT ‘09
MAR ‘95
DS59F7
DS59F4
1

CS5508-BSZ Summary of contents

  • Page 1

    Very Low Power, 16-Bit and 20-Bit A/D Converters Very Low Power, 16-bit & 20-bit A/D Converters Features Very Low Power Consumption l - Single supply +5 V operation: 1 Dual supply ±5 V operation: 3.2 mW Offers superior ...

  • Page 2

    ANALOG CHARACTERISTICS 3.3V ± 5%; VREF+ = 2.5V(external); VREF AGND at AIN; Anal og input channel AIN1+; AIN- = AGND; unless otherwise specified.) (Notes 1, 2) Parameter* Specified Temperature Range Accuracy Linearity Error Differential Nonlinearity Full ...

  • Page 3

    ... VREF = 2.5V CS5506/8; 20-Bit Unit Conversion Factors Symbol out f -3dB t s CS5505/6/7/8 CS5505/6/7 Ω with a source CS5508-S Max Min Typ Max -55 to +125 - 0.0015 0.003 - ±32 - ±8 ± ± ±32 ±16 ±64 ...

  • Page 4

    ANALOG CHARACTERISTICS 3.3V ± 5%; VREF+ = 2.5V (external); VREF- = 0V; f 10nF to AGND at AIN; Analog input channel AIN1+; AIN- = AGND; unless otherwise specified.) (Notes 1, 2) Parameter* Specified Temperature Range Analog Input Analog Input Range: ...

  • Page 5

    DIGITAL CHARACTERISTICS DGND = 0.) All measurements below are performed under static conditions. (Note 2) Parameter High-Level Input Voltage: All Pins Except XIN and M/SLP Low-Level Input Voltage: All Pins Except XIN and M/SLP M/SLP SLEEP Active Threshold High-Level ...

  • Page 6

    SWITCHING CHARACTERISTICS VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; C Parameter Master Clock Frequency: Internal Oscillator: External Clock: Master Clock Duty Cycle Rise Times: Any Digital Input Any Digital Output Fall ...

  • Page 7

    SWITCHING CHARACTERISTICS VD+ = 3.3V ± 5%; VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic pF.) (Note 2) Parameter Master Clock Frequency: Internal Oscillator: External Clock: Master Clock ...

  • Page 8

    XIN XIN/2 CAL CONV STATE Standby XIN XIN/2 A0 CONV DRDY BP/UP STATE Standby ccw t t scl cal Calibration Figure 1. Calibration Timing (Not to Scale) t hca sac t cpw t t scn ...

  • Page 9

    SWITCHING CHARACTERISTICS VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; C Parameter SSC Mode (M/SLP = VD+) Access Time: CS Low to SDATA out (DRDY = low) DRDY falling to MSB (CS ...

  • Page 10

    SWITCHING CHARACTERISTICS 5%; VA ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; C Parameter SSC Mode (M/SLP = VD+) Access Time: CS Low to SDATA out (DRDY = low) DRDY falling to ...

  • Page 11

    XIN XIN/2 CONV CS STATE Standby Conversion DRDY SCLK(o) Hi-Z SDATA(o) Hi-Z STATE (CONV held high) Conversion1 Figure 3. Timing Relationships; SSC Mode (Not to Scale) DRDY CS t csd2 SDATA(o) Hi-Z SCLK(i) DRDY CS t csd2 SDATA(o) Hi-Z SCLK(i) ...

  • Page 12

    RECOMMENDED OPERATING CONDITIONS Parameter DC Power Supplies: Positive Digital (VA+)-(VA-) Positive Analog Negative Analog Analog Reference Voltage (Note 20) (VREF+)-(VREF-) Analog Input Voltage: (Note 21) Unipolar Bipolar Notes: 19. All voltages with r espect to ground. 20. The CS5505/6/7/8 can ...

  • Page 13

    GENERAL DESCRIPTION The CS5505/6/7/8 are very low power mono- lith A/D co nverters designed specifically for measurement of dc signals. The CS5505/7 are 16-bit converters (a four channel and a single channel version). The CS5506/8 are 20-bit ...

  • Page 14

    The calibration state is entered whenever the CAL and CONV pins are high at the same time. The state of the CAL and CONV pins at ...

  • Page 15

    AIN1. The BP/UP pin is not a latched input. The BP/UP pin controls how the output word from the digital filter is processed. In bipolar mode the output word computed by the digital filter is offset by 8000H in the ...

  • Page 16

    ... VREF - 1.5 LSB -0.5 LSB VREF/2 - 0.5 LSB -VREF + 0.5 LSB +0.5 LSB <(-VREF + 0.5 LSB) <(+0.5 LSB) Table 2. Output Coding CS5505/6/7/8 CS5505/6/7/8 CS5506 and CS5508 (20 Bit) Output Bipolar Input Codes Voltage FFFFF >(VREF - 1.5 LSB) FFFFF VREF - 1.5 LSB FFFFE 80000 -0 ...

  • Page 17

    Understanding Converter Calibration Calibration can be performed at any time. A calibration sequence will minimize offset errors and set the gain slope scale factor. The delta- sigma modulator in the converter is a differential modulator. To calibrate out offset error, ...

  • Page 18

    Analog Input Impedance Considerations The analog input of the CS5505/6/7/8 can be modeled as illustrated in Figure 8 (the model ig- nores the multiplexer switch resistance). Capacitors (15 pF each) are used to dynamically sample each of the inputs (AIN+ ...

  • Page 19

    Digital Filter Characteristics The digital filter in the CS5505/6/7/8 is the com- bination of a comb filter and a low pass filter. The comb filter has zeros in its transfer function which are optimally placed to reject line interfer- ence ...

  • Page 20

    If the CS5505/6/7/8 is operated at a clock rate other than 32.768 kHz, the filter characteristics, including the comb filter zeros, will scale with the operating clock frequency. Therefore, opti- mum rejection of line frequency interference will occur with the ...

  • Page 21

    Over the military temperature range (- 55 to +125 °C) the on-chip gate oscillator is designed to work only with a 32.768 kHz crys- tal. The chip will ...

  • Page 22

    Synchronous External-Clocking Mode The serial port operates in the SEC mode when the M/SLP pin is connected to the DGND pin. SDATA is the output pin for the serial data. When CS goes low after new data becomes available (DRDY ...

  • Page 23

    No analog ground pin is re- quired because the inputs for measurement and for the voltage reference are differential and re- quire no ground. In the digital section of the chip the supply current flows into the ...

  • Page 24

    Figure 14 illustrates the System Connection Dia- gram for the CS5505/6 using a single +5V supply. Note that all supply pins are bypassed with 0.1 µF capacitors and that the VD+ digital supply is derived from the VA+ supply. Figure ...

  • Page 25

    Analog Supply Calibration Control Bipolar/ Unipolar Input Select Analog* Signal Sources Signal Ground *Unused analog inputs should be tied to AIN- + Voltage (1) Reference - Note: (1) To use the internal 2.5 volt reference see Figure 6. (2) ...

  • Page 26

    PIN CONNECTIONS* MULTIPLEXER SELECTION INPUT CHIP SELECT CONVERT CALIBRATE CRYSTAL IN CRYSTAL OUT SE RIAL MODE/ SLEEP BIPOLAR/UNIPOLAR DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG RETURN DIFFERENTIAL ANALOG INPUT CHIP SELECT CONVERT CALIBRATE CRYSTAL IN CRYSTAL OUT SERIAL MODE/ ...

  • Page 27

    PIN DESCRIPTIONS Pin numbers for four channel devices are in parentheses. Clock Generator XIN; XOUT - Crystal In; Crystal Out, Pins 4 (5) and 5 (6). A gate inside the chip is connected to these pins and can be used ...

  • Page 28

    Control Input Pins CAL - Calibrate, Pin 3 (4). When taken high the same time that the CONV pin is taken high the converter will perform a self-calibration which includes calibration of the offset and gain scale factors in the ...

  • Page 29

    VD+ - Positive Digital Power, Pin 17 (20). Positive digital supply voltage. Nominally +5 volts or 3.3 volts. DGND - Digital Ground, Pin 16 (19). Digital Ground. Other Connection, Pin 9. Pin should be left floating. SPECIFICATION ...

  • Page 30

    ... CS5506-BSZ (lead free) CS5507-ASZ (lead free) CS5508-BSZ (lead free) ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number CS5505-ASZ (lead free) CS5506-BSZ (lead free) CS5507-ASZ (lead free) CS5508-BSZ (lead free) * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. 30 Liearity Error Channels 16 Bits 0.0030% 20 Bits ...

  • Page 31

    REVISION HISTORY Revision Date F4 MAR 1995 First Final Release F5 AUG 2005 Updated device ordering info. Updated legal notice. Added MSL data.. F7 OCT 2009 Increased minimum Vdiff voltage from 4.5 to 4.75 V. Contacting Cirrus Logic Support For ...

  • Page 32

    NOTES - CS5505/6/7/8 DS59F7 ...

  • Page 33

    Evaluation Board for CS5505/6/7/8 Series of ADC’s Evaluation Board for CS5505/6/7/8 Series of ADCs Features l Operation with on-board 32.768 kHz crystal or off-board clock source l Jumper selectable: - SSC mode; SEC mode; Sleep l DIP Switch Selectable: - ...

  • Page 34

    Introduction The CDB5505/6/7/8 evaluation board provides a quick means of testing the CS5505/6/7/8 series A/D converters. The CS5505/6/7/8 converters require a minimal amount of external circuitry. The evaluation board comes configured with the A/D converter chip operating from a 32.768 ...

  • Page 35

    DS59DB4 DS59DB2 CDB5505/6/7/8 CS5505/6/7 ...

  • Page 36

    A0 and A1 (see Table 1). Once A0 and A1 are selected, the CONV switch (S2-3) must be switched on (closed) and then open to cause the CONV signal to transition low to high. This latches the A0 and ...

  • Page 37

    Figure 3. Top Ground Plane Layer (NOT TO SCALE) DS59DB4 DS59DB2 CDB5505/6/7/8 CS5505/6/7 ...

  • Page 38

    Figure 4. Bottom Trace Layer (NOT TO SCALE CDB5505/6/7/8 CS5505/6/7/8 DS59DB4 DS59DB2 ...

  • Page 39

    DS59DB4 DS59DB2 Figure 5. Silk Screen Layer (NOT TO SCALE) CDB5505/6/7/8 CS5505/6/7 ...

  • Page 40

    REVISION HISTORY Revision Date DB2 MAR 1995 First Release F5 AUG 2005 Updated legal notice. DB4 JUN 2009 Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to ...