AD9246BCPZ-125 Analog Devices Inc, AD9246BCPZ-125 Datasheet

IC ADC 14BIT 125MSPS 48-LFCSP

AD9246BCPZ-125

Manufacturer Part Number
AD9246BCPZ-125
Description
IC ADC 14BIT 125MSPS 48-LFCSP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9246BCPZ-125

Data Interface
Serial, SPI™
Design Resources
Using AD8376 to Drive Wide Bandwidth ADCs for High IF AC-Coupled Appls (CN0002) Driving AD9233/46/54 ADCs in AC-Coupled Baseband Appls (CN0051)
Number Of Bits
14
Sampling Rate (per Second)
125M
Number Of Converters
3
Power Dissipation (max)
425mW
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-VFQFN, CSP Exposed Pad
Resolution (bits)
14bit
Sampling Rate
125MSPS
Input Channel Type
Differential, Single Ended
Supply Voltage Range - Analog
1.7V To 1.9V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD9246-125EBZ - BOARD EVAL FOR 125MSPS AD9246AD9246-105EBZ - BOARD EVAL FOR 105MSPS AD9246
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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Part Number
Manufacturer
Quantity
Price
Part Number:
AD9246BCPZ-125
Manufacturer:
ADI
Quantity:
222
FEATURES
1.8 V analog supply operation
1.8 V to 3.3 V output supply
SNR = 71.7 dBc (72.7 dBFS) to 70 MHz input
SFDR = 85 dBc to 70 MHz input
Low power: 395 mW @ 125 MSPS
Differential input with 650 MHz bandwidth
On-chip voltage reference and sample-and-hold amplifier
DNL = ±0.4 LSB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary, Gray code, or twos complement data format
Clock duty cycle stabilizer
Data output clock
Serial port control
APPLICATIONS
Ultrasound equipment
IF sampling in communications receivers
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes
GENERAL DESCRIPTION
The AD9246 is a monolithic, single 1.8 V supply, 14-bit, 80 MSPS/
105 MSPS/125 MSPS analog-to-digital converter (ADC), featuring
a high performance sample-and-hold amplifier (SHA) and on-chip
voltage reference. The product uses a multistage differential
pipeline architecture with output error correction logic to
provide 14-bit accuracy at 125 MSPS data rates and guarantees
no missing codes over the full operating temperature range.
The wide bandwidth, truly differential SHA allows a variety of
user-selectable input ranges and offsets, including single-ended
applications. It is suitable for multiplexed systems that switch
full-scale voltage levels in successive channels and for sampling
single-channel inputs at frequencies well beyond the Nyquist rate.
Combined with power and cost savings over previously available
ADCs, the AD9246 is suitable for applications in communications,
imaging, and medical ultrasound.
A differential clock input controls all internal conversion cycles.
A duty cycle stabilizer (DCS) compensates for wide variations in
the clock duty cycle while maintaining excellent overall ADC
performance.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Programmable clock and data alignment
Built-in selectable digital test pattern generation
IS-95, CDMA-One, IMT-2000
14-Bit, 80 MSPS/105 MSPS/125 MSPS,
1.8 V Analog-to-Digital Converter
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
SENSE
The digital output data is presented in offset binary, Gray code, or
twos complement formats. A data output clock (DCO) is provided
to ensure proper latch timing with receiving logic.
The AD9246 is available in a 48-lead LFCSP_VQ and is specified
over the industrial temperature range (−40°C to +85°C).
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
REFB
REFT
VREF
VIN+
VIN–
The AD9246 operates from a single 1.8 V power supply
and features a separate digital output driver supply to
accommodate 1.8 V to 3.3 V logic families.
The patented SHA input maintains excellent performance
for input frequencies up to 225 MHz.
The clock DCS maintains overall ADC performance over a
wide range of clock pulse widths.
A standard serial port interface supports various product
features and functions, such as data formatting (offset
binary, twos complement, or Gray coding), enabling the
clock DCS, power-down, and voltage reference mode.
The AD9246 is pin-compatible with the AD9233, allowing
a simple migration from 12 bits to 14 bits.
SELECT
SHA
REF
FUNCTIONAL BLOCK DIAGRAM
AGND
A/D
AVDD
0.5V
MDAC1
©2006 Analog Devices, Inc. All rights reserved.
4
CORRECTION LOGIC
DUTY CYCLE
CLK+
STABILIZER
OUTPUT BUFFERS
Figure 1.
CLOCK
AD9246
1 1/2-BIT PIPELINE
CLK–
8-STAGE
15
8
SELECT
PDWN
MODE
DRVDD
AD9246
A/D
www.analog.com
DRGND
3
OR
DCO
D13 (MSB)
D0 (LSB)
SCLK/DFS
SDIO/DCS
CSB

Related parts for AD9246BCPZ-125

AD9246BCPZ-125 Summary of contents

Page 1

FEATURES 1.8 V analog supply operation 1 3.3 V output supply SNR = 71.7 dBc (72.7 dBFS MHz input SFDR = 85 dBc to 70 MHz input Low power: 395 mW @ 125 MSPS Differential input ...

Page 2

AD9246 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 3 Specifications..................................................................................... 4 DC Specifications ......................................................................... 4 AC Specifications.......................................................................... 5 Digital Specifications ................................................................... 6 Switching ...

Page 3

REVISION HISTORY 8/06—Rev Rev. A Added 80 MSPS .................................................................. Universal Changes to Features ..........................................................................1 Deleted Figures 19, 20, 22, 23 ........................................................11 Deleted Figures 24, 25 29.....................................................12 Deleted Figures 31, 34.....................................................................13 Deleted Figures 37, 38, 40, 41 ...

Page 4

... Rev Page AD9246BCPZ-125 Max Min Typ Max Unit 14 Bits Guaranteed ±0.8 ±0.3 ±0.8 % FSR ±5.0 ±0.6 ±4.2 % FSR ±1.0 ±1.0 LSB ±0.4 LSB ±5.0 ± ...

Page 5

... Full 85 − 25°C −90 25°C −90 25°C 87 25°C 83 25°C 650 Rev Page AD9246 AD9246BCPZ-125 Typ Max Min Typ Max 71.9 71.9 71.9 71.7 69.5 71.6 71.6 70.9 70.8 71.1 71.1 70.8 70.6 68.5 70.6 70 ...

Page 6

... Full Full Full Full Full Full Full Full = 50 μA) Full = 0.5 mA) Full Full Full = 50 μA) Full = 0.5 mA) Full Full Full Rev Page AD9246BCPZ-80/105/125 Min Typ Max CMOS/LVDS/LVPECL 1.2 0.2 6 AVDD − 0.3 AVDD + 1.6 1.1 AVDD 1.2 3.6 0 0.8 −10 +10 −10 +10 8 ...

Page 7

... Full 2 Full 5 Full CLK – – – – – DCO Figure 2. Timing Diagram Rev Page AD9246BCPZ-105 AD9246BCPZ-125 Min Typ Max Min Typ 20 105 20 10 105 10 9.5 8 2.85 4.75 6.65 2.4 4 4.28 4.75 5.23 3.6 4 3.1 3.9 4.8 3.1 3.9 4.4 4.4 3 ...

Page 8

AD9246 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating ELECTRICAL AVDD to AGND −0 +2.0 V DRVDD to DGND −0 +3.9 V AGND to DGND −0 +0.3 V AVDD to DRVDD −3 +2.0 ...

Page 9

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 7. Pin Function Description Pin No. Mnemonic 0, 21, 23, 29, 32, AGND 37, 41 45, 46 (LSB) to D13 (MSB 16, 47 DRGND 8, 17, ...

Page 10

AD9246 EQUIVALENT CIRCUITS VIN Figure 4. Equivalent Analog Input Circuit AVDD 1.2V 10kΩ 10kΩ CLK+ Figure 5. Equivalent Clock Input Circuit DRVDD 1kΩ SDIO/DCS Figure 6. Equivalent SDIO/DCS Input Circuit DRVDD DRGND Figure 7. Equivalent Digital Output Circuit SCLK/DFS OEB ...

Page 11

TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V; DRVDD = 2.5 V; maximum sample rate, DCS enabled internal reference p-p differential input; AIN = −1.0 dBFS; 64k sample 25°C, unless otherwise noted. All figures show ...

Page 12

AD9246 0 125MSPS 225.3MHz @ –1dBFS SNR = 70.3dB (71.3dBFS) –20 ENOB = 11.3 BITS SFDR = 80.4dBc –40 –60 –80 –100 –120 –140 0 15.625 31.250 FREQUENCY (MHz) Figure 18. AD9246-125 Single-Tone FFT with f 0 125MSPS 300.3MHz @ ...

Page 13

SFDR = 85dBc (92dBFS) –40 –60 –80 –100 –120 –140 0 15.625 31.250 FREQUENCY (MHz) Figure 24. AD9246-125 Two-Tone FFT with f IN1 0 125MSPS 169.1MHz @ –7dBFS –20 172.1MHz @ ...

Page 14

AD9246 100 95 SFDR SNR CLOCK FREQUENCY (MSPS) Figure 30. AD9246 Single-Tone SNR/SFDR vs. Clock Frequency (f with f = 2.4 MHz IN 100 SFDR DCS SFDR ...

Page 15

THEORY OF OPERATION The AD9246 architecture consists of a front-end sample-and- hold amplifier (SHA) followed by a pipelined switched capacitor ADC. The quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic. The ...

Page 16

AD9246 DIFFERENTIAL INPUT CONFIGURATIONS Optimum performance is achieved by driving the AD9246 in a differential input configuration. For baseband applications, the AD8138 differential driver provides excellent performance and a flexible interface to the ADC. The output common-mode voltage of the ...

Page 17

P A ANALOG INPUT ANALOG INPUT Table 9. Reference Configuration Summary Selected Mode SENSE Voltage External Reference AVDD Internal Fixed Reference VREF Programmable Reference 0 VREF Internal Fixed Reference AGND to 0.2 V VOLTAGE REFERENCE ...

Page 18

AD9246 VIN+ ADC CORE VIN– VREF 0.1µF 0.1µF SELECT LOGIC SENSE 0.5V AD9246 Figure 42. Internal Reference Configuration VIN+ ADC CORE VIN– VREF 0.1µF 0.1µF R2 SELECT LOGIC SENSE R1 Figure 43. Programmable Reference Configuration If the internal reference of ...

Page 19

MIN-CIRCUITS ADT1–1WT, 1:1Z 0.1µF 0.1µF XFMR CLOCK INPUT 100Ω 50Ω 0.1µF SCHOTTKY 0.1µF DIODES: HSMS2812 Figure 46. Transformer Coupled Differential Clock If a low jitter clock source is not available, another option is to ac-couple a differential PECL signal to ...

Page 20

AD9246 The DCS can be enabled or disabled by setting the SDIO/DCS pin when operating in the external pin mode (see Table 10), or via the SPI, as described in Table 13. Table 10. Mode Selection (External Pin Mode) Voltage ...

Page 21

IAVDD 275 260 TOTAL POWER 245 230 IDRVDD 215 CLOCK FREQUENCY (MSPS) Figure 54. AD9246-80 Power and Current vs. Clock Frequency f Power-Down Mode By asserting the PDWN pin high, the AD9246 is placed in power-down ...

Page 22

AD9246 TIMING The lowest typical conversion rate of the AD9246 is 10 MSPS. At clock rates below 10 MSPS, dynamic performance can degrade. The AD9246 provides latched data outputs with a pipeline delay of 12 clock cycles. Data outputs are ...

Page 23

SERIAL PORT INTERFACE (SPI) The AD9246 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. This provides the user added flexibility and customization, depending ...

Page 24

AD9246 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Each row in the memory map register table has eight address locations. The memory map is roughly divided into three sections: the chip configuration registers map (Address 0x00 to Address 0x02), ...

Page 25

MEMORY MAP REGISTER TABLE Table 15. Memory Map Register Addr. Bit 7 (Hex) Parameter Name (MSB) Bit 6 Chip Configuration Registers 00 chip_port_config 0 LSB first 0 = Off (Default chip_id 02 chip_grade Open Open Device ...

Page 26

AD9246 Addr. Bit 7 (Hex) Parameter Name (MSB) Flexible ADC Functions 10 offset 0D test_io 14 output_mode Output Driver Configuration 00 for DRVDD = 2 3.3 V (Default) 10 for DRVDD = 1 output_phase Output Clock ...

Page 27

LAYOUT CONSIDERATIONS POWER AND GROUND RECOMMENDATIONS When connecting power to the AD9246 recommended that two separate supplies be used: one for analog (AVDD, 1.8 V nominal) and one for digital (DRVDD, 1 3.3 V nominal). If ...

Page 28

AD9246 EVALUATION BOARD The AD9246 evaluation board provides all of the support circuitry required to operate the ADC in its various modes and configurations. The converter can be driven differentially through a double balun configuration (default) or through the AD8352 ...

Page 29

DEFAULT OPERATION AND JUMPER SELECTION SETTINGS The following is a list of the default and optional settings or modes allowed on the AD9246 Rev. A evaluation board. POWER Connect the switching power supply that is supplied in the evaluation kit ...

Page 30

AD9246 1. Remove C1 and C2 in the default analog input path. 2. Populate R3 and R4 with 200 Ω resistors in the analog input path. 3. Populate the optional amplifier input path with all components except R594, R595, and ...

Page 31

SCHEMATICS RC0402 RC0402 RC040 2 RC040 2 RC0402 CC0402 2 HSMS281 2 HSMS281 RC0402 CC0402 CC0402 RC060 3 RC060 3 Figure 60. Evaluation Board Schematic, DUT Analog Inputs Rev Page AD9246 05491-072 CC0402 RC060 3 ...

Page 32

AD9246 Figure 61. Evaluation Board Schematic, DUT, VREF, and Digital Output Interface RC060 3 Rev Page 05491-073 ...

Page 33

CC0402 CC0402 RC0402 RC060 3 CC0402 CC0402 RC060 3 RC060 3 Figure 62. Evaluation Board Schematic, DUT Clock Input CC0402 CC0402 CC0402 RC0402 RC0402 RC0402 RC0402 S0 S10 GND_PAD ...

Page 34

AD9246 RC0603 SDO_CHA RC0603 CSB1_CHA RC0603 SDI_CHA RC0603 SCLK_CHA RC0603 RC0603 RC0603 RC0603 RC0603 1 2 PICVCC PICVCC 3 4 GP1 GP1 5 6 GP0 GP0 7 8 MCLR-GP3 MCLR-GP3 RC060 Figure 63. Evaluation Board Schematic, SPI ...

Page 35

GND GND 1 1 GND GND GND CR500 1 2 Figure 64. Evaluation Board Schematic, Power Supply Inputs Rev Page AD9246 05491-069 TP509 TP512 TP511 TP510 ...

Page 36

AD9246 EVALUATION BOARD LAYOUTS Figure 65. Evaluation Board Layout, Primary Side Figure 66. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev Page ...

Page 37

Figure 67. Evaluation Board Layout, Ground Plane Figure 68. Evaluation Board Layout, Power Plane Rev Page AD9246 ...

Page 38

AD9246 Figure 70. Evaluation Board Layout, Silkscreen Secondary Side (Mirrored Image) Figure 69. Evaluation Board Layout, Silkscreen Primary Side Rev Page ...

Page 39

BILL OF MATERIALS Table 16. Evaluation Board Bill of Materials (BOM) Omit Item Qty. (DNP) Reference Designator 1 1 AD9246CE_REVA 2 24 C1, C2, C509, C510, C511, C512, C514, C515, C516, C517, C528, C530, C532, C533, C538, C539, C540, C542, ...

Page 40

AD9246 Omit Item Qty. (DNP) Reference Designator 29 6 R1, R6, R563, R565, R574, R577 30 5 R2, R5, R561, R562, R571 6 R10, R11, R12, R535, R536, R575 R7, R8, R9, R502, R510, ...

Page 41

... IC SC70 Dual buffer IC SC70 Dual buffer IC 48-pin Buffer/line TSSOP driver DUT 48-pin ADC (AD9246) LFCSP_VQ IC 16-pin Differential LFCSP_VQ amplifier Rev Page AD9246 Supplier/Part Number ADI ADP3339AKCZ-2.5 ADI ADP3339AKCZ-3.3 Microchip PIC12F629 Fairchild NC7WZ16 Fairchild NC7WZ07 Fairchild 74VCX162244 ADI AD9246BCPZ ADI AD8352ACPZ ...

Page 42

... OUTLINE DIMENSIONS PIN 1 INDICATOR 1.00 12° MAX 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range 2 AD9246BCPZ-125 –40°C to +85°C 2 AD9246BCPZRL7-125 –40°C to +85°C AD9246BCPZ-105 2 –40°C to +85°C 2 AD9246BCPZRL7-105 –40°C to +85°C 2 AD9246BCPZ-80 –40°C to +85°C ...

Page 43

NOTES Rev Page AD9246 ...

Page 44

AD9246 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05491-0-8/06(A) Rev Page ...

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