ADC0804LCN/NOPB National Semiconductor, ADC0804LCN/NOPB Datasheet - Page 23

• Manufacturer Part Number: ADC0804LCN/NOPB
• Description: IC ADC 8BIT MPU COMPAT 20-DIP
• Manufacturer: National Semiconductor

Specifications of ADC0804LCN/NOPB

• Number Of Bits: 8
• Number Of Converters: 1
• Power Dissipation (max): 875mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 20-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *ADC0804LCN; *ADC0804LCN/NOPB; ADC0804

Functional Description
Heavy capacitive or DC loading of the clock R pin should be
avoided as this will disturb normal converter operation.
Loads less than 50 pF, such as driving up to 7 A/D converter
clock inputs from a single clock R pin of 1 converter, are
allowed. For larger clock line loading, a CMOS or low power
TTL buffer or PNP input logic should be used to minimize the
loading on the clock R pin (do not use a standard TTL
buffer).
2.7 Restart During a Conversion
If the A/D is restarted (CS and WR go low and return high)
during a conversion, the converter is reset and a new con-
version is started. The output data latch is not updated if the
conversion in process is not allowed to be completed, there-
fore the data of the previous conversion remains in this latch.
The INTR output simply remains at the “1” level.
2.8 Continuous Conversions
For operation in the free-running mode an initializing pulse
should be used, following power-up, to ensure circuit opera-
tion. In this application, the CS input is grounded and the WR
input is tied to the INTR output. This WR and INTR node
should be momentarily forced to logic low following a
power-up cycle to guarantee operation.
2.9 Driving the Data Bus
This MOS A/D, like MOS microprocessors and memories,
will require a bus driver when the total capacitance of the
data bus gets large. Other circuitry, which is tied to the data
bus, will add to the total capacitive loading, even in
TRI-STATE (high impedance mode). Backplane bussing
also greatly adds to the stray capacitance of the data bus.
There are some alternatives available to the designer to
handle this problem. Basically, the capacitive loading of the
data bus slows down the response time, even though DC
specifications are still met. For systems operating with a
relatively slow CPU clock frequency, more time is available
in which to establish proper logic levels on the bus and
therefore higher capacitive loads can be driven (see typical
characteristics curves).
At higher CPU clock frequencies time can be extended for
I/O reads (and/or writes) by inserting wait states (8080) or
using clock extending circuits (6800).
Finally, if time is short and capacitive loading is high, external
bus drivers must be used. These can be TRI-STATE buffers
FIGURE 8. Self-Clocking the A/D
(Continued)
DS005671-17
23
(low power Schottky such as the DM74LS240 series is rec-
ommended) or special higher drive current products which
are designed as bus drivers. High current bipolar bus drivers
with PNP inputs are recommended.
2.10 Power Supplies
Noise spikes on the V
errors as the comparator will respond to this noise. A low
inductance tantalum filter capacitor should be used close to
the converter V
recommended. If an unregulated voltage is available in the
system, a separate LM340LAZ-5.0, TO-92, 5V voltage regu-
lator for the converter (and other analog circuitry) will greatly
reduce digital noise on the V
2.11 Wiring and Hook-Up Precautions
Standard digital wire wrap sockets are not satisfactory for
breadboarding this A/D converter. Sockets on PC boards
can be used and all logic signal wires and leads should be
grouped and kept as far away as possible from the analog
signal leads. Exposed leads to the analog inputs can cause
undesired digital noise and hum pickup, therefore shielded
leads may be necessary in many applications.
A single point analog ground that is separate from the logic
ground points should be used. The power supply bypass
capacitor and the self-clocking capacitor (if used) should
both be returned to digital ground. Any V
pacitors, analog input filter capacitors, or input signal shield-
ing should be returned to the analog ground point. A test for
proper grounding is to measure the zero error of the A/D
converter. Zero errors in excess of
traced to improper board layout and wiring (see section 2.5.1
for measuring the zero error).
3.0 TESTING THE A/D CONVERTER
There are many degrees of complexity associated with test-
ing an A/D converter. One of the simplest tests is to apply a
known analog input voltage to the converter and use LEDs to
display the resulting digital output code as shown in Figure 9 .
For ease of testing, the V
with 2.560 V
be used. This provides an LSB value of 20 mV.
If a full-scale adjustment is to be made, an analog input
voltage of 5.090 V
the V
V
output code is just changing from 1111 1110 to 1111 1111.
This value of V
The digital output LED display can be decoded by dividing
the 8 bits into 2 hex characters, the 4 most significant (MS)
and the 4 least significant (LS). Table 1 shows the fractional
binary equivalent of these two 4-bit groups. By adding the
voltages obtained from the “VMS” and “VLS” columns in
Table 1 , the nominal value of the digital display (when
V
output LED display of 1011 0110 or B6 (in hex), the voltage
values from the table are 3.520 + 0.120 or 3.640 V
voltage values represent the center-values of a perfect A/D
converter. The effects of quantization error have to be ac-
counted for in the interpretation of the test results.
REF
REF
/2 input voltage should then be adjusted until the digital
/2 = 2.560V) can be determined. For example, for an
IN
(+) pin with the V
DC
REF
and a V
CC
DC
/2 should then be used for all the tests.
pin and values of 1 µF or greater are
(5.120–1
CC
CC
IN
(−) pin grounded. The value of the
supply line can cause conversion
supply voltage of 5.12 V
REF
CC
/2 (pin 9) should be supplied
1
⁄
2
supply.
LSB) should be applied to
1
⁄
4
LSB can usually be
REF
/2 bypass ca-
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DC
DC
. These
should