ADC0804LCN/NOPB National Semiconductor, ADC0804LCN/NOPB Datasheet - Page 4

• Manufacturer Part Number: ADC0804LCN/NOPB
• Description: IC ADC 8BIT MPU COMPAT 20-DIP
• Manufacturer: National Semiconductor

Specifications of ADC0804LCN/NOPB

• Number Of Bits: 8
• Number Of Converters: 1
• Power Dissipation (max): 875mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 20-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *ADC0804LCN; *ADC0804LCN/NOPB; ADC0804

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C
CONTROL INPUTS [Note: CLK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately]
V
V
I
I
CLOCK IN AND CLOCK R
V
V
V
V
V
DATA OUTPUTS AND INTR
V
V
V
I
I
I
POWER SUPPLY
I
IN
IN
OUT
SOURCE
SINK
CC
The following specifications apply for V
IN
IN
T
T
H
OUT
OUT
OUT
OUT
OUT
OUT
AC Electrical Characteristics
Symbol
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to Gnd, unless otherwise specified. The separate A Gnd point should always be wired to the D Gnd.
Note 3: A zener diode exists, internally, from V
Note 4: For V
for analog input voltages one diode drop below ground or one diode drop greater than the V
level analog inputs (5V) can cause this input diode to conduct–especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec
allows 50 mV forward bias of either diode. This means that as long as the analog V
be correct. To achieve an absolute 0 V
initial tolerance and loading.
Note 5: Accuracy is guaranteed at f
extended so long as the minimum clock high time interval or minimum clock low time interval is no less than 275 ns.
Note 6: With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process. The
start request is internally latched, see Figure 4 and section 2.0.
+
−
(1)
(0)
(1)
(0)
(0)
(1)
(0)
(1)
(1)
IN
TRI-STATE Output
Capacitance (Data Buffers)
Logical “1” Input Voltage
(Except Pin 4 CLK IN)
Logical “0” Input Voltage
(Except Pin 4 CLK IN)
Logical “1” Input Current
(All Inputs)
Logical “0” Input Current
(All Inputs)
CLK IN (Pin 4) Positive Going
Threshold Voltage
CLK IN (Pin 4) Negative
Going Threshold Voltage
CLK IN (Pin 4) Hysteresis
(V
Logical “0” CLK R Output
Voltage
Logical “1” CLK R Output
Voltage
Logical “0” Output Voltage
Data Outputs
INTR Output
Logical “1” Output Voltage
Logical “1” Output Voltage
TRI-STATE Disabled Output
Leakage (All Data Buffers)
Supply Current (Includes
Ladder Current)
ADC0801/02/03/04LCJ/05
ADC0804LCN/LCWM
(−) V
T
+)−(V
IN
(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see block diagram) which will forward conduct
T
−)
Parameter
CLK
DC
= 640 kHz. At higher clock frequencies accuracy can degrade. For lower clock frequencies, the duty cycle limits can be
to 5 V
CC
DC
CC
to Gnd and has a typical breakdown voltage of 7 V
input voltage range will therefore require a minimum supply voltage of 4.950 V
=5 V
DC
(Continued)
and T
MIN
V
V
V
V
I
V
I
V
I
I
I
V
V
V
V
f
V
and CS =5V
O
O
OUT
OUT
O
CLK
CC
CC
IN
IN
CC
CC
OUT
OUT
OUT
OUT
REF
I
=360 µA
=−360 µA
=−360 µA, V
O
T
=5 V
=0 V
A
=−10 µA, V
=5.25 V
=4.75 V
=4.75 V
=4.75 V
=640 kHz,
=1.6 mA, V
=1.0 mA, V
/2=NC, T
=0 V
=5 V
4
T
Short to Gnd, T
Short to V
MAX
IN
DC
DC
Conditions
does not exceed the supply voltage by more than 50 mV, the output code will
DC
DC
unless otherwise specified.
DC
DC
DC
DC
A
CC
CC
CC
=25˚C
CC
CC
CC
=4.75 V
supply. Be careful, during testing at low V
=4.75 V
=4.75 V
=4.75 V
, T
A
A
=25˚C
=25˚C
DC
.
DC
DC
DC
DC
Min
2.0
2.7
1.5
0.6
2.4
2.4
4.5
4.5
9.0
−1
−3
−0.005
0.005
Typ
3.1
1.8
1.3
1.1
1.9
16
DC
5
6
over temperature variations,
CC
levels (4.5V), as high
Max
7.5
0.8
3.5
2.1
2.0
0.4
0.4
0.4
1.8
2.5
15
1
3
mA
mA
Units
µA
µA
µA
µA
V
V
V
V
V
V
V
V
V
V
V
mA
mA
pF
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC