IC ADC 12BIT 210MSPS 48-QFN

ADS6128IRGZT

Manufacturer Part NumberADS6128IRGZT
DescriptionIC ADC 12BIT 210MSPS 48-QFN
ManufacturerTexas Instruments
ADS6128IRGZT datasheet
 


Specifications of ADS6128IRGZT

Number Of Bits12Sampling Rate (per Second)210M
Data InterfaceSerial, ParallelNumber Of Converters1
Power Dissipation (max)687mWVoltage Supply SourceAnalog and Digital
Operating Temperature-40°C ~ 85°CMounting TypeSurface Mount
Package / Case48-VFQFN Exposed PadNumber Of Elements1
Resolution12BitArchitecturePipelined
Sample Rate210MSPSInput PolarityBipolar
Input TypeVoltageRated Input Volt±1V
Differential InputYesPower Supply RequirementAnalog and Digital
Single Supply Voltage (typ)3.3VSingle Supply Voltage (min)3V
Single Supply Voltage (max)3.6VDual Supply Voltage (typ)Not RequiredV
Dual Supply Voltage (min)Not RequiredVDual Supply Voltage (max)Not RequiredV
Power Dissipation687mWDifferential Linearity Error±0.2LSB(Typ)
Integral Nonlinearity Error±1LSB(Typ)Operating Temp Range-40C to 85C
Operating Temperature ClassificationIndustrialMountingSurface Mount
Pin Count48Package TypeVQFN EP
Input Signal TypeDifferentialLead Free Status / RoHS StatusLead free / RoHS Compliant
Other names296-23837-2  
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.....................................................................................................................................................
14/12-Bit, 250/210 MSPS ADCs With DDR LVDS and Parallel CMOS Outputs
FEATURES
1
Maximum Sample Rate: 250 MSPS
14-Bit Resolution – ADS614X
12-Bit Resolution – ADS612X
687 mW Total Power Dissipation at 250 MSPS
Double Data Rate (DDR) LVDS and Parallel
CMOS Output Options
Programmable Fine Gain up to 6dB for
SNR/SFDR Trade-Off
DC Offset Correction
Supports Input Clock Amplitude Down to 400
mV
Differential
PP
Internal and External Reference Support
48-QFN Package (7mm × 7mm)
Pin Compatible with ADS5547 Family
APPLICATIONS
Multicarrier, Wide Band-Width
Communications
Wireless Multi-carrier Communications
Infrastructure
Software Defined Radio
Power Amplifier Linearization
802.16d/e
Test and Measurement Instrumentation
High Definition Video
Medical Imaging
Radar Systems
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ADS6149/ADS6129
ADS6148/ADS6128
SLWS211B – JULY 2008 – REVISED OCTOBER 2008
DESCRIPTION
ADS614X (ADS612X) is a family of 14-bit (12-bit) A/D
converters with sampling rates up to 250 MSPS. It
combines high dynamic performance and low power
consumption in a compact 48 QFN package. This
makes it well-suited for multicarrier, wide band-width
communications applications.
ADS614X/2X has fine gain options that can be used
to improve SFDR performance at lower full-scale
input ranges. It includes a dc offset correction loop
that can be used to cancel the ADC offset. Both DDR
LVDS (Double Data Rate) and parallel CMOS digital
output interfaces are available. At lower sampling
rates, the ADC automatically operates at scaled down
power with no loss in performance.
It includes internal references while the traditional
reference pins and associated decoupling capacitors
have been eliminated. Nevertheless, the device can
also be driven with an external reference. The device
is specified over the industrial temperature range
(–40°C to 85°C).
250 MSPS
ADS614X
ADS6149
14-Bit Family
ADS612X
ADS6129
12-Bit Family
Copyright © 2008, Texas Instruments Incorporated
210 MSPS
ADS6148
ADS6128

ADS6128IRGZT Summary of contents

  • Page 1

    ... Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C). 250 MSPS ADS614X ADS6149 14-Bit Family ADS612X ADS6129 12-Bit Family Copyright © 2008, Texas Instruments Incorporated 210 MSPS ADS6148 ADS6128 ...

  • Page 2

    ... Product Folder Link(s): ..................................................................................................................................................... CLOCKGEN DDR 14-Bit ADC Serializer Control Reference Interface ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com DDR LVDS Interface CLKOUTP CLKOUTM D0_D1_P D0_D1_M D2_D3_P D2_D3_M D4_D5_P D4_D5_M D6_D7_P D6_D7_M D8_D9_P D8_D9_M D10_D11_P D10_D11_M D12_D13_P D12_D13_M OVR_SDOUT B0095-06 Copyright © 2008, Texas Instruments Incorporated ...

  • Page 3

    ... ADS612X BLOCK DIAGRAM CLKP CLKM INP Sample and Hold INM VCM ADS6129/28 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): CLOCKGEN DDR 12-Bit ADC Serializer Control Reference Interface ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ...

  • Page 4

    ... AZ6149 ADS6149IRGZT Tape and reel ADS6148IRGZR AZ6148 ADS6148IRGZT ADS6129IRGZR AZ6129 ADS6129IRGZT Tape and reel ADS6128IRGZR AZ6128 ADS6128IRGZT = 25.41° C/W (0LFM air flow), JA VALUE –0 3.9 –0 2.2 –0 3.3 –1.5 to 1.8 –0.3 to 2.0 –0.3V to minimum ( 3.6, AVDD + 0.3V ) –0.3V to AVDD + 0.3V – ...

  • Page 5

    ... Differential load resistance between the LVDS output pairs (LVDS mode Operating free-air temperature A (1) See the Theory of Operation in the application section. Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SLWS211B – JULY 2008 – REVISED OCTOBER 2008 (1) input amplitude PP (1) input amplitude ...

  • Page 6

    ... Copyright © 2008, Texas Instruments Incorporated UNIT V PP MΩ pF MHz mV/V %FS % ...

  • Page 7

    ... Signal to noise ratio, LVDS SINAD Signal to noise and distortion ratio, LVDS ENOB, Effective number of bits DNL Differential non-linearity INL Integrated non-linearity Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): = –40° MIN MAX Fin = 20 MHz Fin = 80 MHz Fin = 100 MHz Fin = 170 MHz ...

  • Page 8

    ... T MIN MAX ADS6149/ADS6129 250 MSPS MIN signal on AVDD supply PP ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com = 85°C, AVDD = 3.3 V, DRVDD = 1.8 V ADS6148/ADS6128 210 MSPS TYP MAX MIN TYP MAX 88 Copyright © 2008, Texas Instruments Incorporated UNIT dBc dBc dBc dBc dBc dBFS clock cycles dB ...

  • Page 9

    ... With external 100 Ω termination Dn_Dn+1_P Dn_Dn+1_P Dn_Dn+1_M Dn_Dn+1_M V OCM V OCM GND GND Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TEST CONDITIONS (1) All digital inputs support 1.8V and 3.3V CMOS logic levels VHIGH = 3.3V VHIGH = 3.3V VLOW = 0V VLOW = 0V (4) ...

  • Page 10

    ... Copyright © 2008, Texas Instruments Incorporated UNIT ns fs rms 1 s clock cycles clock cycles ...

  • Page 11

    ... SAMPLING FREQUENCY, MSPS 150 125 <100 Enable LOW SPEED mode 1 ≤ Fs ≤ 100 Enable LOW SPEED mode ( 1/Sampling frequency Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SLWS211B – JULY 2008 – REVISED OCTOBER 2008 SETUP TIME, ns MIN TYP MAX 1.0 1 ...

  • Page 12

    ... Submit Documentation Feedback Product Folder Link(s): ..................................................................................................................................................... N+4 N+3 N+2 18 Clock Cycles N–17 N–16 N–15 18 Clock Cycles* N–17 N–16 N–15 N–14 Figure 2. Latency Diagram ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com N+20 N+19 N+ PDI N+1 N+2 t PDI N–1 N N+1 N+2 Copyright © 2008, Texas Instruments Incorporated O T0105-09 ...

  • Page 13

    ... Dn (2) Dn+1 – Bits D1, D3, D5, ... Input Clock Output Clock Output Data Input Clock Output Data *Dn – Bits D0, D1, D2, ... Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): CLKP CLKM CLKOUTP CLKOUTM Dn_Dn+1_P, (1) Dn Dn_Dn+1_M – Bits D0, D2, D4,... Figure 3. LVDS Mode Timing ...

  • Page 14

    ... Table 1. Parallel Pin Functions CONTROLS MODES Data format and LVDS/CMOS output interface. Internal or external reference, low speed mode enable CLKOUT edge programmability. Global power-down (ADC, internal references and output buffers are powered down) ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com Table 3 to Copyright © 2008, Texas Instruments Incorporated ...

  • Page 15

    ... CMOS output (5/8)AVDD Offset binary data and parallel CMOS output AVDD Offset binary data and DDR LVDS output Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): Table 3. The voltage levels can be easily derived, by using a resistor Figure 5 ...

  • Page 16

    ... This initializes internal registers to their default values and then self-resets the <RESET> bit to LOW. In this case the RESET pin is kept LOW. 16 Submit Documentation Feedback Product Folder Link(s): ..................................................................................................................................................... Table 6. MODE – ANALOG CONTROL PIN DESCRIPTION (5/8) AVDD GND (3/8) AVDD ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com AVDD To Parallel Pin S0321-01 th SCLK falling edge Copyright © 2008, Texas Instruments Incorporated ...

  • Page 17

    ... The device outputs the contents (D7-D0) of the selected register on OVR_SDOUT pin. d. The external controller can latch the contents at the falling edge of SCLK enable register writes, reset register bit <SERIAL READOUT> Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): Register Address ...

  • Page 18

    ... Register Address (A7:A0) = 0x3F SDATA SCLK SEN OVR_SDOUT Pin OVR_SDOUT functions as serial readout (<SERIAL READOUT> Submit Documentation Feedback Product Folder Link(s): ..................................................................................................................................................... Register Data (D7:D0 (Don't Care Figure 7. Serial Readout ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com Register Data (D7:D0) = 0x01 Copyright © 2008, Texas Instruments Incorporated T0386-01 ...

  • Page 19

    ... A7–A0 IN HEX D7 <RESET> 00 Software Reset (1) Multiple functions in a register can be programmed in a single write operation. Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TEST CONDITIONS t 1 RESET t 2 SEN Figure 8. Reset Timing Diagram REGISTER FUNCTIONS REF> 0 Internal or external reference <LVDS CMOS> 0 ...

  • Page 20

    ... DFS pin controls LVDS or CMOS interface selection 10 DDR LVDS interface 11 Parallel CMOS interface 20 Submit Documentation Feedback Product Folder Link(s): ..................................................................................................................................................... <RESET> 0 Software Reset <REF> ADS6149/ADS6129 ADS6148/ADS6128 <ENABLE 0 LOW SPEED 0 MODE> <PDN 0 <STANDBY> GLOBAL> Copyright © 2008, Texas Instruments Incorporated www.ti.com D0 <SERIA L READO UT> <PDN OBUF> ...

  • Page 21

    ... E) A7–A0 IN HEX D2,D1 <DATA FORMAT> 00 DFS pin controls data format selection 10 2's complement 11 Offset binary F) A7–A0 IN HEX 51 52 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s <CLKOUT POSN> Output clock position control <DATA FORMAT> 2s complement or offset binary D7 D6 ...

  • Page 22

    ... Submit Documentation Feedback Product Folder Link(s): ..................................................................................................................................................... D6 <ENABLE OFFSET CORR> Offset correction enable <FINE GAIN> ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com <OFFSET CORR TC> Offset correction time constant Copyright © 2008, Texas Instruments Incorporated D0 0 ...

  • Page 23

    ... Mid-code + 31 LSB 011110 Mid-code + 30 LSB 011101 Mid-code + 29 LSB .... 000000 Mid-code 111111 Mid-code - 1 LSB 111110 Mid-code - 2 LSB .... 100000 Mid-code - 32 LSB Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s clock cycle from code 0 to code 4095 ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – ...

  • Page 24

    ... Thermal Pad Pad is connected to DRGND Thermal Pad ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com DRGND 36 35 DRVDD D0_D1_P 34 D0_D1_M RESET 30 29 SCLK SDATA 28 SEN 27 26 AVDD AGND 25 P0023-12 36 DRGND 35 DRVDD RESET SCLK 29 SDATA 28 27 SEN AVDD 26 AGND 25 P0023-13 Copyright © 2008, Texas Instruments Incorporated ...

  • Page 25

    ... MODE. In the system board using ADS61x9/x8, the MODE pin can be routed to a digital controller. This will avoid board modification while migrating to the next generation ADC. Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DESCRIPTION Table 3 for detailed information ...

  • Page 26

    ... NAME NO. PINS DRVDD 1.8 V Digital and output buffer supply DRGND 1, 36, PAD I 2 Digital and output buffer ground See Figure not connect and Figure 10 26 Submit Documentation Feedback Product Folder Link(s): ..................................................................................................................................................... DESCRIPTION ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com Copyright © 2008, Texas Instruments Incorporated ...

  • Page 27

    ... CLKM AGND Figure 11. PIN CONFIGURATION (CMOS MODE) – ADS6149/48 DRGND DRVDD OVR_SDOUT UNUSED CLKOUT DFS OE AVDD AGND CLKP CLKM AGND Figure 12. PIN CONFIGURATION (CMOS MODE) – ADS6129/28 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): 1 Pad is connected to DRGND Thermal Pad ...

  • Page 28

    ... READOUT> functions as serial register readout pin when <SERIAL READOUT> 1.8 V Digital and output buffer supply Digital and output buffer ground Unused pin in CMOS mode Do not connect ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com Table 4 for detailed Table 6 for Copyright © 2008, Texas Instruments Incorporated ...

  • Page 29

    ... SFDR = –91 dBFS −40 −60 −80 −100 −120 −140 −160 − Frequency − MHz Figure 17. Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): 0 SFDR = 94.6 dBc SINAD = 73.3 dBFS −20 SNR = 73.4 dBFS THD = 90.2 dBc −40 −60 −80 −100 −120 −140 − ...

  • Page 30

    ... CMOS 100 150 200 250 300 350 400 450 500 f − Input Frequency − MHz IN Figure 20. SINAD vs GAIN 100 150 200 250 300 350 400 450 500 f − Input Frequency − MHz IN Figure 22. Copyright © 2008, Texas Instruments Incorporated PP G008 G010 ...

  • Page 31

    ... PERFORMANCE vs AVDD SUPPLY 60.1 MHz IN 94 DRV = 1 SFDR 88 86 SNR 2.9 3.0 3.1 3.2 3.3 3.4 AV − Supply Voltage − Figure 25. Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s MHz MHz 1.35 1.40 − − Common-Mode Voltage of Analog Inputs − ...

  • Page 32

    ... INPUT CLOCK AMPLITUDE SFDR SNR 0.70 1.20 1.70 2.20 2.70 Input Clock Amplitude − Figure 28. PERFORMANCE vs VCM VOLTAGE SFDR SNR 1.40 1.45 1.50 1.55 1.60 1.65 1.70 V − VCM Voltage − V VCM Figure 30. G019 Copyright © 2008, Texas Instruments Incorporated www.ti.com G016 G018 ...

  • Page 33

    ... Frequency − MHz Figure 36. Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): LVDS output interface (unless otherwise noted) 0 SFDR = 90.75 dBc SFDR = 92.3 dBc SINAD = 73.13 dBFS SINAD = 72.9 dBFS −20 SNR = 73.25 dBFS SNR = 73 dBFS THD = 87 ...

  • Page 34

    ... CMOS 100 150 200 250 300 350 400 450 500 f − Input Frequency − MHz IN Figure 39. SINAD vs GAIN 100 150 200 250 300 350 400 450 500 f − Input Frequency − MHz IN Figure 41. Copyright © 2008, Texas Instruments Incorporated PP G027 G029 ...

  • Page 35

    ... Input Amplitude − dBFS Figure 42. PERFORMANCE vs AVDD SUPPLY 60.1 MHz IN 94 DRV = 1 SNR 2.9 3.0 3.1 3.2 3.3 3.4 AV − Supply Voltage − Figure 44. Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s 60.1 MHz MHz −10 0 1.35 1. G030 ...

  • Page 36

    ... INPUT CLOCK AMPLITUDE SFDR SNR 0.70 1.20 1.70 2.20 Input Clock Amplitude − Figure 47. PERFORMANCE vs VCM VOLTAGE SFDR SNR 1.40 1.45 1.50 1.55 1.60 1.65 1.70 V − VCM Voltage − V VCM Figure 49. G038 Copyright © 2008, Texas Instruments Incorporated G035 G037 ...

  • Page 37

    ... Frequency − MHz Figure 55. Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): LVDS output interface (unless otherwise noted) 0 SFDR = 94.87 dBc SFDR = 87.8 dBc SINAD = 70.73 dBFS SINAD = 70.5 dBFS −20 SNR = 70.77 dBFS SNR = 70.6 dBFS THD = 89 ...

  • Page 38

    ... CMOS 100 150 200 250 300 350 400 450 500 f − Input Frequency − MHz IN Figure 58. SINAD vs GAIN 100 150 200 250 300 350 400 450 500 f − Input Frequency − MHz IN Figure 60. Copyright © 2008, Texas Instruments Incorporated PP G046 G048 ...

  • Page 39

    ... PERFORMANCE vs AVDD SUPPLY 60.1 MHz IN 94 DRV = 1 SFDR SNR 82 80 2.9 3.0 3.1 3.2 3.3 3.4 AV − Supply Voltage − Figure 63. Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s MHz MHz −10 0 1.35 1.40 V − Common-Mode Voltage of Analog Inputs − ...

  • Page 40

    ... INPUT CLOCK AMPLITUDE SFDR SNR 0.70 1.20 1.70 2.20 2.70 Input Clock Amplitude − Figure 66. PERFORMANCE vs VCM VOLTAGE SFDR SNR 1.40 1.45 1.50 1.55 1.60 1.65 1.70 V − VCM Voltage − V VCM Figure 68. G057 Copyright © 2008, Texas Instruments Incorporated www.ti.com G054 G056 ...

  • Page 41

    ... Frequency − MHz Figure 74. Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): LVDS output interface (unless otherwise noted) 0 SFDR = 90.8 dBc SFDR = 92.5 dBc SINAD = 70.6 dBFS SINAD = 70.5 dBFS −20 SNR = 70.7 dBFS SNR = 70.6 dBFS THD = 87 ...

  • Page 42

    ... CMOS 100 150 200 250 300 350 400 450 500 f − Input Frequency − MHz IN Figure 77. SINAD vs GAIN 100 150 200 250 300 350 400 450 500 f − Input Frequency − MHz IN Figure 79. Copyright © 2008, Texas Instruments Incorporated PP G065 G067 ...

  • Page 43

    ... Input Amplitude − dBFS Figure 80. PERFORMANCE vs AVDD SUPPLY 60.1 MHz IN 94 DRV = 1 SNR 2.9 3.0 3.1 3.2 3.3 3.4 AV − Supply Voltage − Figure 82. Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s MHz MHz −10 0 1.35 1. G068 60.1 MHz ...

  • Page 44

    ... INPUT CLOCK AMPLITUDE SFDR SNR 0.70 1.20 1.70 2.20 Input Clock Amplitude − Figure 85. PERFORMANCE vs VCM VOLTAGE SFDR SNR 1.40 1.45 1.50 1.55 1.60 1.65 1.70 V − VCM Voltage − V VCM Figure 87. G076 Copyright © 2008, Texas Instruments Incorporated G073 G075 ...

  • Page 45

    ... Input Frequency − MHz IN Figure 89. 100 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): LVDS output interface (unless otherwise noted) 1.0 C 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 100 ...

  • Page 46

    ... Figure 92. SFDR Contour Plot (0 dB gain 300 400 500 f - Input Frequency - MHz SFDR - dBc Figure 93. SFDR Contour Plot (6 dB gain) ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com differential clock amplitude, 50% clock duty 350 400 450 500 M0049- 600 700 800 M0049-18 Copyright © 2008, Texas Instruments Incorporated ...

  • Page 47

    ... Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s 150 200 250 300 f - Input Frequency - MHz SNR - dBFS Figure 94. SNR Contour Plot (0 dB gain ...

  • Page 48

    ... Cpar2 0.5 pF Resr 3 pF 200 W Cpar1 0. 100 Cpar2 0.5 pF Resr 200 W Figure 96. Analog Input Equivalent Circuit ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com Sampling Switch Sampling Capacitor Ron 15 W Csamp 2 pF Ron 10 W Csamp Ron Sampling Capacitor Sampling Switch Copyright © 2008, Texas Instruments Incorporated ...

  • Page 49

    ... Figure 97. ADC Analog Input Resistance (Rin) Across Frequency Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): Figure 98 show the impedance (Zin = Rin || Cin) looking into the ADC input 200 300 400 500 600 f - Frequency - MHz ...

  • Page 50

    ... Submit Documentation Feedback Product Folder Link(s): ..................................................................................................................................................... 200 300 400 500 600 700 f - Frequency - MHz Figure 99 Figure 100), the capacitance used in the R-C-R is ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com 800 900 1000 and Figure 100 – one optimized for low Copyright © 2008, Texas Instruments Incorporated ...

  • Page 51

    ... The full-scale input range of the converter can be controlled in the external reference mode as explained below. The internal or external reference modes can be selected by programming the serial interface register bit <REF>. Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ...

  • Page 52

    ... This allows using transformer-coupled drive circuits for sine wave clock or ac-coupling for LVPECL, LVDS clock sources. 52 Submit Documentation Feedback Product Folder Link(s): ..................................................................................................................................................... INTREF EXTREF Figure 101. Reference Section Equation 2. ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com Internal Reference REFM REFP S0165-09 Copyright © 2008, Texas Instruments Incorporated (2) ...

  • Page 53

    ... CLKP Differential Sine-Wave or PECL or LVDS Clock Input 0 CLKM Figure 103. Differential Clock Driving Circuit Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): Ceq 5 kW VCM 5 kW Ceq ~ pF, equivalent input capacitance of clock buffer Figure 102. Internal Clock Buffer CMOS Clock Input S0167-10 Figure 104 ...

  • Page 54

    ... Time constant (TCCLK), number of clock cycles 256 k 512 128 M 256 M 512 M RESERVED RESERVED RESERVED RESERVED ADS6149/ADS6129 ADS6148/ADS6128 Full-Scale 1.78 1.59 1.42 1.26 1.12 1.00 Time constant, sec (=TCCLK x 1/Fs) ( 134 ms 268 ms 536 ms 1.1 s 2.2 s – – – – Copyright © 2008, Texas Instruments Incorporated www.ti.com ...

  • Page 55

    ... Externally, they can be driven from separate supplies or from a single supply. DIGITAL OUTPUT INFORMATION ADS614X/2X provides 14-bit/12-bit data and an output clock synchronized with the data. Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): Offset Correction Disabled Offset Correction Enabled ...

  • Page 56

    ... Data bits D0, D1 D0_D1_M P D2_D3_ Data bits D2, D3 D2_D3_M D4_D5_P Data bits D4, D5 D4_D5_M D6_D7_P Data bits D6, D7 D6_D7_M D8_D9_P Data bits D8, D9 D8_D9_M D10_D11_P Data bits D10, D11 D10_D11_M Figure 107. 12-Bit ADC LVDS Outputs Copyright © 2008, Texas Instruments Incorporated ...

  • Page 57

    ... The buffer output impedance behaves like a source-side series termination. By absorbing reflections from the receiver end, it helps to improve signal integrity. Note that this internal termination cannot be disabled and its value cannot be changed. Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): CLKOUTP ...

  • Page 58

    ... These timings can be used to delay the input clock appropriately and use it to capture the data (see 58 Submit Documentation Feedback Product Folder Link(s): ..................................................................................................................................................... ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com OUTP External 100- Load W OUTM Rout S0374-01 Figure 4). Copyright © 2008, Texas Instruments Incorporated ...

  • Page 59

    ... For a negative input overdrive, the output code is 0x0000 in offset binary output format and 0x2000 in 2s complement output format. Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): Pins ...

  • Page 60

    ... So necessary to solder the exposed pad to the ground plane for best thermal and electrical performance. For detailed information, see the application notes for QFN Layout Guidelines (SLOA122) and QFN/SON PCB Attachment (SLUA271). 60 Submit Documentation Feedback Product Folder Link(s): ..................................................................................................................................................... ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com Copyright © 2008, Texas Instruments Incorporated ...

  • Page 61

    ... Effective Number of Bits (ENOB) – The ENOB is a measure of the converter performance as compared to the theoretical limit based on quantization noise. Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s TOTAL ...

  • Page 62

    ... It is typically expressed in dBc. 62 Submit Documentation Feedback Product Folder Link(s): ..................................................................................................................................................... is the change in supply voltage and ΔVout is the resultant change of the SUP ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com ( the power of the S (6) (7) OUT (8) Copyright © 2008, Texas Instruments Incorporated ...

  • Page 63

    ... PACKAGING INFORMATION Orderable Device (1) Package Type Package Status ADS6128IRGZ25 ACTIVE VQFN ADS6128IRGZR ACTIVE VQFN ADS6128IRGZRG4 ACTIVE VQFN ADS6128IRGZT ACTIVE VQFN ADS6128IRGZTG4 ACTIVE VQFN ADS6129IRGZ25 ACTIVE VQFN ADS6129IRGZR ACTIVE VQFN ADS6129IRGZRG4 ACTIVE VQFN ADS6129IRGZT ACTIVE VQFN ADS6129IRGZTG4 ACTIVE VQFN ADS6148IRGZ25 ACTIVE ...

  • Page 64

    Orderable Device (1) Package Type Package Status ADS6149IRGZRG4 ACTIVE VQFN ADS6149IRGZT ACTIVE VQFN ADS6149IRGZTG4 ACTIVE VQFN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device ...

  • Page 65

    ... TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Type Drawing ADS6128IRGZR VQFN RGZ ADS6128IRGZT VQFN RGZ ADS6129IRGZR VQFN RGZ ADS6129IRGZT VQFN RGZ ADS6148IRGZR VQFN RGZ ADS6148IRGZT VQFN RGZ ADS6149IRGZR VQFN RGZ ADS6149IRGZT VQFN RGZ PACKAGE MATERIALS INFORMATION ...

  • Page 66

    ... Device Package Type ADS6128IRGZR VQFN ADS6128IRGZT VQFN ADS6129IRGZR VQFN ADS6129IRGZT VQFN ADS6148IRGZR VQFN ADS6148IRGZT VQFN ADS6149IRGZR VQFN ADS6149IRGZT VQFN PACKAGE MATERIALS INFORMATION Package Drawing Pins SPQ Length (mm) RGZ 48 2500 RGZ 48 250 RGZ 48 2500 RGZ 48 250 RGZ ...

  • Page 67

    ...

  • Page 68

    ... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’ ...