LTC2442IG#PBF Linear Technology, LTC2442IG#PBF Datasheet
LTC2442IG#PBF
Specifications of LTC2442IG#PBF
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LTC2442IG#PBF Summary of contents
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... V the 1X speed mode the fi rst conversion following a new speed/resolution or channel selection is valid. , LTC and LT are registered trademarks of Linear Technology Corporation. No Latency ∆Σ trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. ...
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LTC2442 ABSOLUTE AXI U RATI GS (Notes 1, 2) Supply Voltage ( GND ....................... –0. Analog Input Pins Voltage to GND ......................................–0. Reference Input Pins Voltage to GND ......................................–0.3V to ...
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ELECTRICAL CHARACTERISTICS temperature range, otherwise specifi cations are at T PARAMETER CONDITIONS + Negative Full-Scale Error REF + REF Negative Full-Scale Error Drift 2.5V ≤ REF + SEL Total Unadjusted Error 5V ≤ ≤ REF Input ...
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LTC2442 U U DIGITAL I PUTS A D DIGITAL OUTPUTS full operating temperature range, otherwise specifi cations are at T SYMBOL PARAMETER V High Level Input Voltage IH CS EXT, SDI O V Low Level Input Voltage IL ...
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CHARACTERISTICS range, otherwise specifi cations are SYMBOL PARAMETER f External Oscillator Frequency Range EOSC t External Oscillator High Period HEO t External Oscillator Low Period LEO t Conversion Time CONV f Internal ...
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LTC2442 W U TYPICAL PERFOR A CE CHARACTERISTICS Integral Non-Linearity 2.048V INCM 4.096V REF – –1 –2 –3 –4 ...
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CTIO S SCK (Pin 1): Bidirectional Digital Clock Pin. In internal serial clock operation mode, SCK is used as a digital output for the internal serial interface clock during the data output period. In the ...
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LTC2442 CTIO S MUXOUTA (Pin 27): Multiplexer Output. Must tie to +INA amplifi er input (Pin 25). COM (Pin 28): The common negative input (SEL single ended multiplexer confi gurations. The voltage on CH0-CH3 and ...
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CTIO AL BLOCK DIAGRA V MUXOUTB +INB CC GND CH0 CH1 CH2 MUX CH3 COM MUXOUTA +INA –INA TEST CIRCUITS SDO 1.69k Hi Hi ...
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LTC2442 U U APPLICATIO S I FOR ATIO Once CS is pulled LOW, the device begins outputting the conversion result. There is no latency in the conversion result while operating in the 1X mode. The data output corresponds to the ...
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U U APPLICATIO S I FOR ATIO Reference Voltage Range The LTC2442 ΔΣ converter accepts a truly differential external reference voltage. The absolute/common mode + voltage specifi cation for the REF the entire range from GND For ...
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LTC2442 U U APPLICATIO S I FOR ATIO the fi rst falling edge of SCK. The fi nal data bit (Bit 0) is shifted out on the falling edge of the 31st SCK and may be latched on the rising ...
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U U APPLICATIO S I FOR ATIO Table 3. Channel Selection MUX ADDRESS SGL ODD/SIGN ...
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LTC2442 U U APPLICATIO S I FOR ATIO Chip Select Input (CS) The active LOW chip select, CS (Pin 35), is used to test the conversion status and to enable the data output transfer as described in the previous sections. ...
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U U APPLICATIO S I FOR ATIO selected speed/resolution and input channel is valid. This is identical to the operation of the LTC2440 and LTC2444 through LTC2449. While operating in the 2X mode, the device performs a running average of ...
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LTC2442 U U APPLICATIO S I FOR ATIO External Serial Clock, Single Cycle Operation (SPI/MICROWIRE Compatible) This timing mode uses an external serial clock to shift out the conversion result and a CS signal to monitor and control the state ...
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U U APPLICATIO S I FOR ATIO As described above, CS may be pulled LOW at any time in order to monitor the conversion status on the SDO pin. Typically, CS remains LOW during the data output state. However, the ...
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LTC2442 U U APPLICATIO S I FOR ATIO External Serial Clock, 2-Wire I/O This timing mode utilizes a 2-wire serial I/O interface. The conversion result is shifted out of the device by an externally generated serial clock (SCK) signal, see ...
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U U APPLICATIO S I FOR ATIO Internal Serial Clock, Single Cycle Operation This timing mode uses an internal serial clock to shift out the conversion result and a CS signal to monitor and control the state of the conversion ...
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LTC2442 U U APPLICATIO S I FOR ATIO If CS remains LOW longer than t EOCtest edge of SCK will occur and the conversion result is serially shifted out of the SDO pin. The data output cycle begins on this ...
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U U APPLICATIO S I FOR ATIO Internal Serial Clock, 3-Wire I/O, Continuous Conversion This timing mode uses a 3-wire, all output (SCK and SDO) interface. The conversion result is shifted out of the device by an internally generated serial ...
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LTC2442 U U APPLICATIO S I FOR ATIO Normal Mode Rejection and Antialiasing One of the advantages delta-sigma ADCs offer over conventional ADCs is on-chip digital fi ltering. Combined with a large oversampling ratio, the LTC2442 signifi cantly simplifi es ...
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U U APPLICATIO S I FOR ATIO grounded set by the on-chip oscillator 1.8MHz ±5% (over supply and temperature variations OSR of 32,768, the fi rst NULL ...
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LTC2442 U U APPLICATIO S I FOR ATIO Input Bandwidth and Frequency Rejection The combined effect of the internal SINC the digital and analog autocalibration circuits determines the LTC2442 input bandwidth and rejection characteristics. The digital fi lter’s response can ...
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U U APPLICATIO S I FOR ATIO Optimizing Linearity While the integrated op-amp has rail-to-rail input range, in order to achieve parts-per-million linearity performance, the input range and op-amp supply voltages must be con- sidered. Input levels within 1.25V of ...
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LTC2442 U U APPLICATIO S I FOR ATIO The LTC2442 breaks new ground in high impedance input ΔΣ ADCs. The input buffer is optimized to make driving the ADC as easy as possible, while overcoming many of the limitations typical ...
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U U APPLICATIO S I FOR ATIO Low Power Operation The integrated buffers have a supply current of 1mA total, greatly reducing the total power consumption when the ADC is operated at a low duty cycle. The typical approach to ...
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LTC2442 U U APPLICATIO S I FOR ATIO IN1 IN OUT 5V LT1236N U3 5 GND TRIM 40k – LTC2050HV –5V V ...
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U U APPLICATIO S I FOR ATIO Details of the Conversion and Autozero Process The LTC2442 performs automatic offset cancellation for each conversion. This is accomplished by taking the aver- age of two “half-conversions” with the inputs applied in opposite ...
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LTC2442 U U APPLICATIO S I FOR ATIO The amplifi ers take approximately 50µs to settle for a full-scale input voltage. This does not affect accuracy in either 2x mode or 1x mode for OSR values between 256 to 32768. ...
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... FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. ...
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... Noise at 880Hz, 200nV RMS 0.0005% INL 3.5kHz Output Rate ● www.linear.com 0 –2. – V 74HC4053 U4 – 0.1 –2. 2. 1.8k 6 R22 INH –2. GND Noise P-P Noise 0.01Hz to 10Hz P-P Noise at 6.9Hz, RMS LT 1105 • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 2005 2442f ...