AD9265BCPZ-80 Analog Devices Inc, AD9265BCPZ-80 Datasheet
AD9265BCPZ-80
Specifications of AD9265BCPZ-80
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AD9265BCPZ-80 Summary of contents
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FEATURES SNR = 79.0 dBFS @ 70 MHz and 125 MSPS SFDR = 93 dBc @ 70 MHz and 125 MSPS Low power: 373 mW @ 125 MSPS 1.8 V analog supply operation 1.8 V CMOS or LVDS output supply ...
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AD9265 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Product Highlights ........................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications ..................................................................................... 4 ADC DC Specifications ............................................................... 4 ADC AC Specifications ................................................................. 5 ...
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GENERAL DESCRIPTION The AD9265 is a 16-bit, 125 MSPS analog-to-digital converter (ADC). The AD9265 is designed to support communications applications where high performance combined with low cost, small size, and versatility is desired. The ADC core features a multistage, differential ...
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... Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. 4 Standby power is measured with a dc input, the CLK pins (CLK+, CLK−) inactive (set to AVDD or AGND). 1 AD9265BCPZ-80 AD9265BCPZ-105 Temp Min Typ Max ...
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... MHz 140 MHz 200 MHz IN With On-Chip Dither (AIN @ −23 dBFS 2.4 MHz MHz 140 MHz 200 MHz IN 2 AD9265BCPZ-80 AD9265BCPZ-105 Temp Min Typ Max Min 25°C 80.2 25°C 79.7 Full 78.7 78.2 25°C 78.4 25°C 77.1 25°C 79.6 25°C 79.6 Full 78 ...
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... SYNC INPUT Logic Compliance Internal Bias Input Voltage Range High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance Input Resistance 2 AD9265BCPZ-80 AD9265BCPZ-105 Temp Min Typ Max Min 25°C −106 25°C −106 Full − ...
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Parameter 1 LOGIC INPUT (CSB) High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance 2 LOGIC INPUT (SCLK/DFS) High Level Input Voltage Low Level Input Voltage High Level Input ...
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... See the Input Clock Divider section for additional information on using the DCS with the input clock divider. 4 Additional DCO delay can be added by writing to Bit 0 through Bit 4 in SPI Register 0x17 (see Table 17). 5 Wake-up time is defined as the time required to return to normal operation from power-down mode. 1 AD9265BCPZ-80 AD9265BCPZ-105 Temp Min Typ Max ...
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TIMING SPECIFICATIONS Table 5. Parameter Conditions SYNC TIMING REQUIREMENTS t SYNC to rising edge of CLK setup time SSYNC t SYNC to rising edge of CLK hold time HSYNC SPI TIMING REQUIREMENTS t Setup time between the data and the ...
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AD9265 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Electrical AVDD to AGND DRVDD to AGND SVDD to AGND VIN+, VIN− to AGND CLK+, CLK− to AGND SYNC to AGND VREF to AGND SENSE to AGND VCM to AGND RBIAS to AGND ...
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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS NOTES 1. DNC = DO NOT CONNECT. 2. Table 8. Pin Function Descriptions (Parallel CMOS Mode) Pin No. Mnemonic Type ADC Power Supplies 13, 20, 29 DRVDD Supply 4, 5, 34, 36, 45 AVDD Supply ...
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AD9265 Pin No. Mnemonic Type 19 D9 Output 21 D10 Output 22 D11 Output 23 D12 Output 24 D13 Output 25 D14 Output 26 D15 (MSB) Output 27 OR Output 8 DCO Output SPI Control 31 SCLK/DFS Input 30 SDIO/DCS ...
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NOTES 1. DNC = DO NOT CONNECT. 2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE Table 9. Pin Function Descriptions (Interleaved Parallel LVDS Mode) Pin No. Mnemonic Type ADC Power Supplies 13, 20, 29 DRVDD Supply 4, ...
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AD9265 Pin No. Mnemonic Type 22 D10/11+ Output 21 D10/11− Output 24 D12/13+ Output 23 D12/13− Output 26 D14/15+ Output 25 D14/15− Output 28 OR+ Output 27 OR− Output 8 DCO+ Output 7 DCO− Output SPI Control 31 SCLK/DFS Input ...
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TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, SVDD = 1.8 V, sample rate = 125 MSPS, DCS enabled, 1.0 V internal reference p-p differential input, VIN = −1.0 dBFS, and 32k sample ...
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AD9265 120 110 100 SFDRFS (DITHER OFF) 90 SNRFS (DITHER OFF) 80 SNRFS (DITHER ON) 70 –100 –90 –80 –70 –60 –50 –40 INPUT AMPLITUDE (dBFS) Figure 12. AD9265-80 Single-Tone SNR/SFDR vs. Input Amplitude ( MHz With ...
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SNR = 78.8dB (79.8dBFS) –20 SFDR = 91dBc –40 –60 SECOND HARMONIC –80 THIRD HARMONIC –100 –120 –140 FREQUENCY (MHz) Figure 18. AD9265-105 Single-Tone FFT with f 0 105MSPS 70.1MHz @ ...
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AD9265 120 110 100 SFDRFS (DITHER OFF) 90 SNRFS (DITHER OFF) 80 SNRFS (DITHER ON) 70 –100 –90 –80 –70 –60 –50 –40 INPUT AMPLITUDE (dBFS) Figure 24. AD9265-105 Single-Tone SNR/SFDR vs. Input Amplitude ( MHz with ...
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SNR = 78.0dB (79.0dBFS) –20 SFDR = 88dBc –40 –60 SECOND HARMONIC –80 THIRD HARMONIC –100 –120 –140 FREQUENCY (MHz) Figure 30. AD9265-125 Single-Tone FFT with f 0 125MSPS 30.3MHz ...
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AD9265 0 125MSPS 70.1MHz @ –6dBFS SNR = 73.5dB (79.5dBFS) –20 SFDR = 98dBc –40 –60 –80 SECOND THIRD HARMONIC HARMONIC –100 –120 –140 FREQUENCY (MHz) Figure 36. AD9265-125 Single-Tone FFT with f IN Dither Enabled ...
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SFDR @ –40°C 95 SFDR @ +25° SNR @ –40° SNR @ +25°C SNR @ +85° 100 150 200 INPUT FREQUENCY (MHz) Figure 42. AD9265-125 Single-Tone SNR/SFDR vs. Input Frequency (f ...
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AD9265 105 100 95 SFDR 90 85 SNR SAMPLE RATE (MSPS) Figure 48. AD9265-125 Single-Tone SNR/SFDR vs. Sample Rate (f with f = 70.1 MHz IN 450,000 400,000 350,000 300,000 250,000 ...
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EQUIVALENT CIRCUITS VIN+ OR VIN– Figure 53. Equivalent Analog Input Circuit AVDD 0.9V 10kΩ 10kΩ CLK+ Figure 54. Equivalent Clock Input Circuit DRVDD PAD Figure 55. Digital Output AVDD 350Ω SENSE Figure 56. Equivalent SENSE Circuit VREF Figure 57. Equivalent ...
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AD9265 350Ω PDWN Figure 61. Equivalent PDWN Circuit DRVDD 350Ω OEB Figure 62. Equivalent OEB Input Circuit LVDS OR LVDS_RS 26kΩ Figure 63. Equivalent DITHER, LVDS, and LVDS_RS Input Circuit 26kΩ Rev Page AVDD DITHER, ...
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THEORY OF OPERATION With the AD9265, the user can sample any f segment from dc to 200 MHz, using appropriate low-pass or band-pass filtering at the ADC inputs with little loss in ADC performance. Operation to 300 MHz analog input ...
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AD9265 Dither The AD9265 has an optional dither mode that can be selected either through the SPI bus or by using the DITHER pin. Dithering is the act of injecting a known but random amount of white noise, commonly referred ...
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SNR is a key parameter, differential double balun coupling is the recommended input configuration (see Figure 68). In this configuration, the input is ac-coupled and the CML is provided to each input through a 33 Ω resistor. These resistors ...
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AD9265 VOLTAGE REFERENCE A stable and accurate voltage reference is built into the AD9265. The input range can be adjusted by varying the reference voltage applied to the AD9265, using either the internal reference or an externally applied reference voltage. ...
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External Reference Operation The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift charac- teristics. Figure 73 shows the typical drift characteristics of the internal reference in 1.0 V ...
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AD9265 0.1µF CLOCK INPUT AD95xx LVDS DRIVER 0.1µF CLOCK INPUT 50kΩ 50kΩ Figure 78. Differential LVDS Sample Clock (Up to Rated Sample Rate) In some applications, it may be acceptable to drive the sample clock inputs with a single-ended CMOS ...
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Treat the clock input as an analog signal in cases in which aperture jitter may affect the dynamic range of the AD9265. To avoid modulating the clock signal with digital noise, separate power supplies for clock drivers from the ADC ...
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AD9265 DIGITAL OUTPUTS The AD9265 output drivers can be configured to interface with 1.8 V CMOS logic families. The AD9265 can also be configured for LVDS outputs using a DRVDD supply voltage of 1.8 V. The AD9265 defaults to CMOS ...
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BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST The AD9265 includes built-in test features designed to enable verification of the integrity of the part as well as facilitate board level debugging. A BIST (built-in self-test) feature is included that verifies the integrity ...
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AD9265 SERIAL PORT INTERFACE (SPI) The AD9265 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and ...
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CONFIGURATION WITHOUT THE SPI In applications that do not interface to the SPI control registers, the SDIO/DCS pin and the SCLK/DFS pin serve as standalone CMOS-compatible control pins. When the device is powered up assumed that the user ...
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AD9265 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Each row in the memory map register table has eight bit locations. The memory map is roughly divided into four sections: the chip configuration registers (Address 0x00 to Address 0x02); the ...
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MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 17 are not currently supported for this device. Table 17. Memory Map Registers Addr. Register (Hex) Name Bit 7 (MSB) Bit 6 Chip Configuration Registers ...
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AD9265 Addr. Register (Hex) Name Bit 7 (MSB) Bit 6 0x14 Output Drive Output mode strength type 0 = ANSI LVDS 0 = CMOS 1 = reduced 1 = LVDS LVDS 0x16 Clock phase Invert DCO Open control clock 0x17 ...
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MEMORY MAP REGISTER DESCRIPTIONS For additional information about functions controlled in Register 0x00 to Register 0xFF, see AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Sync Control (Register 0x100) Bits[7:3]—Reserved These bits are reserved. Bit 2—Clock Divider Next ...
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AD9265 APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting design and layout of the AD9265 as a system recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements that are needed for ...
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... Model Temperature Range AD9265BCPZ-125 −40°C to +85°C AD9265BCPZRL7-125 −40°C to +85°C AD9265BCPZ-105 −40°C to +85°C AD9265BCPZRL7-105 −40°C to +85°C AD9265BCPZ-80 −40°C to +85°C AD9265BCPZRL7-80 −40°C to +85°C AD9265-125EBZ AD9265-105EBZ AD9265-80EBZ RoHS Compliant Part. 7.10 0.60 MAX 7 ...
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AD9265 NOTES Rev Page ...
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NOTES Rev Page AD9265 ...
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AD9265 NOTES ©2009–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08502-0-1/10(A) Rev Page ...