LTC2449CUHF Linear Technology, LTC2449CUHF Datasheet - Page 16

• Manufacturer Part Number: LTC2449CUHF
• Description: IC ADC 24BIT HI SPEED 38QFN
• Manufacturer: Linear Technology

Specifications of LTC2449CUHF

• Number Of Bits: 24
• Sampling Rate (per Second): 8k
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 40mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 38-WFQFN, Exposed Pad
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

(EXTERNAL)
LTC2444/LTC2445/
LTC2448/LTC2449
APPLICATIO S I FOR ATIO
External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)
This timing mode uses an external serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 4.
The serial clock mode is selected by the EXT pin. To select
the external serial clock mode, EXT must be tied low.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
EOC = 1 (BUSY = 1) while a conversion is in progress and
EOC = 0 (BUSY = 0) if the device is in the sleep state.
Independent of CS, the device automatically enters the low
power sleep state once the conversion is complete.
16
BUSY
SDO
SCK
SDI
CS
CONVERSION
TEST EOC
TEST EOC
U
SLEEP
Hi-Z
U
1
BIT 31
EOC
1
Figure 4. External Serial Clock, Single Cycle Operation
W
2
BIT 30
“0”
0
0.1V TO V
REFERENCE
ANALOG
INPUTS
VOLTAGE
3
BIT 29
SIG
1µF
4.5V TO 5.5V
EN
CC
4
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21
•
•
•
•
•
•
MSB
SGL
U
28
29
30
15
16
23
8
7
V
REF
REF
CH0
CH7
CH8
CH15
COM
CC
5
•
•
•
•
•
•
LTC2448
ODD
+
–
BUSY
6
SDO
GND
SCK
SDI
CS
A2
F
O
37
2
1,4,5,6,31,32,33,39
7
34
38
35
36
When the device is in the sleep state (EOC = 0), its
conversion result is held in an internal static shift regis-
ter. The device remains in the sleep state until the first
rising edge of SCK is seen. Data is shifted out the SDO pin
on each falling edge of SCK. This enables external circuitry
to latch the output on the rising edge of SCK. EOC can be
latched on the first rising edge of SCK and the last bit of
the conversion result can be latched on the 32nd rising
edge of SCK. On the 32nd falling edge of SCK, the device
begins a new conversion. SDO goes HIGH (EOC = 1) and
BUSY goes HIGH indicating a conversion is in progress.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z
and BUSY monitored for the completion of a conversion.
A1
8
DATA OUTPUT
4-WIRE
SPI INTERFACE
A0
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
9
OSR3
10
OSR2
11
OSR1
12
BIT 20 BIT 19
OSR0 TWOX
13
14
32
BIT 0
LSB
CONVERSION
2444589fb
Hi-Z
2444 F05