LTC2449CUHF#TR Linear Technology, LTC2449CUHF#TR Datasheet - Page 17

• Manufacturer Part Number: LTC2449CUHF#TR
• Description: IC ADC 24BIT HI SPEED 38QFN
• Manufacturer: Linear Technology

Specifications of LTC2449CUHF#TR

• Number Of Bits: 24
• Sampling Rate (per Second): 8k
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 40mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 38-WFQFN, Exposed Pad
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status on the SDO pin.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the fifth falling edge and the
32nd falling edge of SCK, see Figure 5. On the rising edge
of CS, the device aborts the data output state and imme-
diately initiates a new conversion. Thirteen serial input
data bits are required in order to properly program the
speed/resolution and input channel. If the data output
CONVERSION
(EXTERNAL)
BUSY
SDO
SCK
SDI
CS
SLEEP
U
1
DATA OUTPUT
DON'T CARE
U
5
Figure 5. External Serial Clock, Reduced Output Data Length
0.1V TO V
REFERENCE
W
ANALOG
INPUTS
CONVERSION
VOLTAGE
1µF
4.5V TO 5.5V
Hi-Z
CC
•
•
•
•
•
•
28
29
30
15
16
23
8
7
1
BIT 31
U
EOC
V
REF
REF
CH0
CH7
CH8
CH15
COM
CC
•
•
•
•
•
•
LTC2448
+
–
2
BIT 30
“0”
BUSY
GND
SDO
SCK
SDI
CS
F
3
O
DON'T CARE
BIT 29
SIG
37
2
1,4,5,6,31,32,33,39
34
38
35
36
DATA OUTPUT
sequence is aborted prior to the 13th rising edge of SCK,
the new input data is ignored, and the previously selected
speed/resolution and channel are used for the next con-
version cycle. This is useful for systems not requiring all
32 bits of output data, aborting an invalid conversion
cycle or synchronizing the start of a conversion. If a new
channel is being programmed, the rising edge of CS must
come after the 14th falling edge of SCK in order to store
the data input sequence.
4
BIT 28 BIT 27 BIT 26 BIT 25
MSB
4-WIRE
SPI INTERFACE
5
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
6
LTC2444/LTC2445/
LTC2448/LTC2449
Hi-Z
CONVERSION
TEST EOC
DON'T CARE
SLEEP
2444 F06
17
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