LTC2449CUHF#PBF Linear Technology, LTC2449CUHF#PBF Datasheet - Page 19

• Manufacturer Part Number: LTC2449CUHF#PBF
• Description: IC ADC 24BIT 38-QFN
• Manufacturer: Linear Technology

Specifications of LTC2449CUHF#PBF

• Number Of Bits: 24
• Sampling Rate (per Second): 8k
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 40mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 38-WFQFN, Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIO S I FOR ATIO
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 7.
In order to select the internal serial clock timing mode, the
EXT pin must be tied HIGH.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state. Alternatively,
BUSY (Pin 2) may be used to monitor the status of the
conversion in progress. BUSY is HIGH during the conver-
BUSY
SCK
SDO
SDI
CS
CONVERSION
TEST EOC
TEST EOC
DON'T CARE
U
SLEEP
<t
Hi-Z
EOC(TEST)
U
1
BIT 31
EOC
1
0.1V TO V
REFERENCE
2
ANALOG
INPUTS
BIT 30
VOLTAGE
“0”
0
W
Figure 7. Internal Serial Clock, Single Cycle Operation
1µF
4.5V TO 5.5V
3
CC
BIT 29
SIG
EN
•
•
•
•
•
•
28
29
30
15
16
23
8
7
4
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21
MSB
V
REF
REF
CH0
CH7
CH8
CH15
COM
SGL
CC
•
•
•
•
•
•
LTC2448
+
–
U
5
ODD
BUSY
SDO
GND
SCK
SDI
CS
F
O
6
37
2
1,4,5,6,31,32,33,39
A2
34
38
35
36
7
A1
4-WIRE
SPI INTERFACE
sion and goes LOW at the conclusion. It remains LOW until
the result is read from the device.
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state and enter the data output
state if CS remains LOW. In order to prevent the device
from exiting the low power sleep state, CS must be pulled
HIGH before the first rising edge of SCK. In the internal
SCK timing mode, SCK goes HIGH and the device begins
outputting data at time t
(if EOC = 0) or t
during the falling edge of EOC). The value of t
500ns. If CS is pulled HIGH before time t
remains in the sleep state. The conversion result is held in
the internal static shift register.
8
DATA OUTPUT
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
A0
9
OSR3
10
OSR2
EOCtest
11
OSR1
LTC2444/LTC2445/
LTC2448/LTC2449
12
BIT 20 BIT 19
OSR0 TWOX
after EOC goes LOW (if CS is LOW
EOCtest
13
14
after the falling edge of CS
DON'T CARE
EOCtest
32
BIT 0
LSB
, the device
CONVERSION
EOCtest
Hi-Z
19
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2444 F08
is