LTC2449CUHF#PBF Linear Technology, LTC2449CUHF#PBF Datasheet - Page 21

• Manufacturer Part Number: LTC2449CUHF#PBF
• Description: IC ADC 24BIT 38-QFN
• Manufacturer: Linear Technology

Specifications of LTC2449CUHF#PBF

• Number Of Bits: 24
• Sampling Rate (per Second): 8k
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 40mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 38-WFQFN, Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIO S I FOR ATIO
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
This timing mode uses a 2-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 9. CS may be permanently tied to ground, simplify-
ing the user interface or isolation barrier. The internal
serial clock mode is selected by tying EXT HIGH.
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1) and BUSY = 1. Once the
conversion is complete, SCK, BUSY and SDO go LOW
(EOC = 0) indicating the conversion has finished and the
BUSY
SDO
SCK
SDI
CS
DON'T CARE
CONVERSION
U
U
BIT 31
EOC
1
1
BIT 30
SLEEP
“0”
2
0
0.1V TO V
REFERENCE
ANALOG
INPUTS
VOLTAGE
W
Figure 9. Internal Serial Clock, Continuous Operation
BIT 29
1µF
SIG
4.5V TO 5.5V
EN
3
CC
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21
•
•
•
•
•
•
MSB
SGL
28
29
30
15
16
23
4
8
7
V
REF
REF
CH0
CH7
CH8
CH15
COM
CC
•
•
•
•
•
•
LTC2448
ODD
U
+
–
5
BUSY
GND
SDO
SCK
SDI
CS
F
A2
6
O
37
2
1,4,5,6,31,32,33,39
38
34
35
36
A1
7
DATA OUTPUT
device has entered the low power sleep state. The part
remains in the sleep state a minimum amount of time
(≈500ns) then immediately begins outputting data. The
data output cycle begins on the first rising edge of SCK and
ends after the 32nd rising edge. Data is shifted out the SDO
pin on each falling edge of SCK. The internally generated
serial clock is output to the SCK pin. This signal may be
used to shift the conversion result into external circuitry.
EOC can be latched on the first rising edge of SCK and the
last bit of the conversion result can be latched on the 32nd
rising edge of SCK. After the 32nd rising edge, SDO goes
HIGH (EOC = 1) indicating a new conversion is in progress.
SCK remains HIGH during the conversion.
4-WIRE
SPI INTERFACE
A0
8
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
OSR3
9
OSR2
10
OSR1
11
LTC2444/LTC2445/
BIT 20 BIT 19
OSR0 TWOX
LTC2448/LTC2449
12
13
14
DON'T CARE
BIT 0
LSB
32
2444 F10
CONVERSION
21
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