LTC1750IFW Linear Technology, LTC1750IFW Datasheet

IC ADC 14BIT 80MSPS SMPL 48TSSOP

LTC1750IFW

Manufacturer Part Number
LTC1750IFW
Description
IC ADC 14BIT 80MSPS SMPL 48TSSOP
Manufacturer
Linear Technology
Datasheet

Specifications of LTC1750IFW

Number Of Bits
14
Sampling Rate (per Second)
80M
Data Interface
Parallel
Number Of Converters
1
Power Dissipation (max)
1.69W
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-TFSOP (0.240", 6.10mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LTC1750IFW#PBF
Manufacturer:
LINEAR/凌特
Quantity:
20 000
FEATURES
BLOCK DIAGRA
APPLICATIO S
Sample Rate: 80Msps
500MHz Full Power Bandwidth S/H
Direct IF Sampling Up to 500MHz
PGA Front End (2.25V
75.5dB SNR and 90dB SFDR (PGA = 0)
73dB SNR and 90dB SFDR (PGA = 1)
No Missing Codes
Single 5V Supply
Power Dissipation: 1.45W
Two Pin Selectable Reference Values
Two’s Complement or Offset Binary Outputs
Out-of-Range Indicator
Data Ready Output Clock
Pin-for-Pin Family
48-Pin TSSOP Package
Telecommunications
Receivers
Cellular Base Stations
Spectrum Analysis
Imaging Systems
MRI
Tomography
ANALOG INPUT
DIFFERENTIAL
1.125V
4.7 F
SENSE
PGA
A
A
V
IN
IN
CM
+
U
SELECT
RANGE
2V
REF
P-P
W
or 1.35V
BUFFER
80Msps, 14-Bit ADC with a 2.25V Differential Input Range
CIRCUIT
P-P
S/H
Input Range)
DIFF AMP
0.1 F
REFLB
1 F
PIPELINED ADC
14-BIT
REFHA
4.7 F
DESCRIPTIO
The LTC
signed for digitizing wide dynamic range signals up to
frequencies of 500MHz. The input range of the ADC can be
optimized with the on-chip PGA sample-and-hold circuit
and flexible reference circuitry.
The LTC1750 has a highly linear sample-and-hold circuit
with a bandwidth of 500MHz. The SFDR is 82dB with an
input frequency of 250MHz. Ultralow jitter of 0.12ps
allows undersampling of IF frequencies with minimal
degradation in SNR. DC specs include 3LSB INL and no
missing codes.
The digital interface is compatible with 5V, 3V, 2V and
LVDS logic systems. The ENC and ENC inputs may be
driven differentially from PECL, GTL and other low swing
logic families or from single-ended TTL or CMOS. The low
noise, high gain ENC and ENC inputs may also be driven
by a sinusoidal signal without degrading performance. A
separate output power supply can be operated from 0.5V
to 5V, making it easy to connect directly to any low voltage
DSPs or FIFOs.
The 48-pin TSSOP package with a flow-through pinout
simplifies the board layout.
REFLA
, LTC and LT are registered trademarks of Linear Technology Corporation.
1 F
0.1 F
REFHB
®
1750 is an 80Msps, 14-bit A/D converter de-
CORRECTION
LOGIC AND
REGISTER
SHIFT
ENCODE INPUT
DIFFERENTIAL
CONTROL LOGIC
ENC
Wide Bandwidth ADC
14
ENC
U
LATCHES
OUTPUT
MSBINV
OV
V
GND
1750 BD
OGND
DD
14-Bit, 80Msps
DD
OF
D13
D0
CLKOUT
1 F
0.1 F
1 F
LTC1750
0.1 F
0.5V TO 5V
1 F
5V
RMS
1
1750f

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LTC1750IFW Summary of contents

Page 1

... DSPs or FIFOs. The 48-pin TSSOP package with a flow-through pinout simplifies the board layout. , LTC and LT are registered trademarks of Linear Technology Corporation. CORRECTION LOGIC AND S/H 14-BIT ...

Page 2

... External Reference (V = 1.125V) SENSE V = 1.125V, PGA = 0 SENSE CONDITIONS 4.75V V 5.25V DD + – 0 < < Sample Mode ENC < ENC Hold Mode ENC > ENC – + 1.5V < < INFORMATION ORDER PART TOP VIEW NUMBER OGND LTC1750CFW 46 D13 45 D12 LTC1750IFW 44 D11 D10 OGND 37 GND 36 GND OGND 26 CLKOUT 25 ...

Page 3

ACCURACY SYMBOL PARAMETER SNR Signal-to-Noise Ratio SFDR Spurious Free Dynamic Range S/( Signal-to-(Noise + Distortion) Ratio THD Total Harmonic Distortion IMD Intermodulation Distortion Sample-and-Hold Bandwidth TER AL REFERE CE ...

Page 4

LTC1750 U U DIGITAL I PUTS A D DIGITAL OUTPUTS operating temperature range, otherwise specifications are at T SYMBOL PARAMETER V High Level Input Voltage IH V Low Level Input Voltage IL I Digital Input Current IN C Digital Input ...

Page 5

ELECTRICAL CHARACTERISTICS Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to GND (unless otherwise noted). Note 3: When these pin voltages are ...

Page 6

LTC1750 W U TYPICAL PERFOR A CE CHARACTERISTICS 8192 Point FFT 30.2MHz, IN –10dB, PGA = 0 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 ...

Page 7

W U TYPICAL PERFOR A CE CHARACTERISTICS 8192 Point FFT 250.2MHz, IN –10dB, PGA = 1 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 ...

Page 8

LTC1750 W U TYPICAL PERFOR A CE CHARACTERISTICS SNR vs Input Frequency and Amplitude, PGA = 1 74 –20dB 73 72 –10dB 71 –1dB 400 500 100 200 300 INPUT FREQUENCY (MHz) 1750 ...

Page 9

CTIO S SENSE (Pin 1): Reference Sense Pin. GND selects 0.7V. V selects 1.125V. When V DD and 1.125V used as V SENSE REF is V /PGA gain. REF V ...

Page 10

LTC1750 DIAGRA • N ANALOG INPUT ENC t 7 DATA t 6 CLKOUT APPLICATIO S I FOR ATIO DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The ...

Page 11

U U APPLICATIO S I FOR ATIO Spurious Free Dynamic Range (SFDR) Spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and DC. This value is expressed in ...

Page 12

LTC1750 U U APPLICATIO S I FOR ATIO In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output ...

Page 13

U U APPLICATIO S I FOR ATIO Input Drive Circuits The LTC1750 requires differential drive for the analog inputs. A balanced input drive will minimize even order harmonics that are due to nonlinear behavior of the input drive circuits and ...

Page 14

LTC1750 U U APPLICATIO S I FOR ATIO 5V SINGLE-ENDED INPUT + 2V 1/2 25 RANGE 1/2 LT1818 – 100 + 25 1/2 LT1818 – 500 500 Figure 4. Differential Drive with Op Amps signal conversion. Note that the two ...

Page 15

U U APPLICATIO S I FOR ATIO 4.7 F 10k LTC1750 1V SENSE 1 F 10k Figure 6a. 2V Range ADC 2V 2. LT1790-1.25 0 10k 1, 2 Figure 6b. 2V ...

Page 16

LTC1750 U U APPLICATIO S I FOR ATIO ANALOG INPUT 0.1 F CLOCK INPUT 50 ENC THRESHOLD 2V ENC 0.1 F Figure 8a. Single-Ended ENC Drive, Not Recommended for Low Jitter Maximum and Minimum Encode Rates The ...

Page 17

U U APPLICATIO S I FOR ATIO DATA FROM LATCH Output Loading As with all high speed/high resolution converters the digital output loading can affect the performance. The digital outputs of the LTC1750 should drive a minimal capacitive load to ...

Page 18

LTC1750 U U APPLICATIO S I FOR ATIO REFLA. These capacitors should be as close to the device as possible (1.5mm or less). Size 0402 ceramic capacitors are recomended. The large 4.7 F capacitor between REFHA and REFLA can be ...

Page 19

... MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights Package 48-Lead Plastic TSSOP (6.1mm) ...

Page 20

... Rail-to-Rail Input and Output DC to 3GHz, 17dBm IIP3, Integrated LO Buffer 1.5GHz to 2.5GHz, 21.5dBm IIP3, Integrated LO Quadrature Generator 800MHz to 3GHz, 17dBm IIP3, Integrated LO Buffer 600MHz to 3GHz, 25dBm IIP3, Integrated LO Buffer www.linear.com 1750f LT/TP 0204 1K • PRINTED IN THE USA LINEAR TECHNOLOGY CORPORATION 2004 ...

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