AD7782BRU-REEL Analog Devices Inc, AD7782BRU-REEL Datasheet - Page 4

• Manufacturer Part Number: AD7782BRU-REEL
• Description: IC ADC 24BIT 2CH 16-TSSOP T/R
• Manufacturer: Analog Devices Inc

Specifications of AD7782BRU-REEL

• Rohs Status: RoHS non-compliant
• Number Of Bits: 24
• Sampling Rate (per Second): 19.79
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 3.9mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)

AD7782
TIMING CHARACTERISTICS
Parameter
t
t
t
t
t
t
t
t
t
Slave Mode Timing
Master Mode Timing
NOTES
1
2
3
4
5
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
1
ADC
2
3
4
5
8
9
10
Sample tested during initial release to ensure compliance. All input signals are specified with t
See Figure 2.
These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V
SCLK active edge is falling edge of SCLK.
back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part
and as such are independent of external bus loading capacitances.
3
5
t
t
t
t
t
6
7
6
7
11
Limit at T
(B Version)
30.5176
50.54
0
0
60
80
2 × t
0
60
80
10
80
0
10
80
100
100
t
t
t
3t
1
1
1
/2
/2
/2
1
/2
ADC
MIN
1, 2
, T
TO OUTPUT
MAX
(V
Logic 1 = V
DD
PIN
= 2.7 V to 3.6 V or V
50pF
ms typ
Unit
µs typ
ns min
ns min
ns max
ns max
ns typ
ns min
ns max
ns max
ns min
ns max
ns min
ns min
ns max
ns min
ns min
µs typ
µs typ
µs min
µs max
DD
unless otherwise noted.)
I
I
SINK
SOURCE
DD
R
= 4.75 V to 5.25 V; GND = 0 V; XTAL = 32.768 kHz; Input Logic 0 = 0 V,
(1.6mA WITH V
= t
100 A WITH V
( 200 A WITH V
F
100 A WITH V
Conditions/Comments
Crystal Oscillator Period
19.79 Hz Update Rate
CH1/CH2 Select to CS Setup Time
CS Falling Edge to DOUT Active
V
V
Channel Settling Time
SCLK Active Edge to Data Valid Delay
V
V
Bus Relinquish Time after CS Inactive Edge
CS Rising Edge to SCLK Inactive Edge Hold Time
SCLK Inactive to DOUT High
SCLK High Pulsewidth
SCLK Low Pulsewidth
SCLK High Pulsewidth
SCLK Low Pulsewidth
DOUT Low to First SCLK Active Edge
= 5 ns (10% to 90% of V
DD
DD
DD
DD
1.6V
= 4.75 V to 5.25 V
= 2.7 V to 3.6 V
= 4.75 V to 5.25 V
= 2.7 V to 3.6 V
DD
DD
= 5V
= 3V)
DD
DD
= 5V
= 3V)
DD
OL
) and timed from a voltage level of 1.6 V.
or V
OH
limits.
4
4