AD7450ABRM-REEL7 Analog Devices Inc, AD7450ABRM-REEL7 Datasheet - Page 23

IC ADC 12BIT W/DIFF INP 8-MSOP

AD7450ABRM-REEL7

Manufacturer Part Number
AD7450ABRM-REEL7
Description
IC ADC 12BIT W/DIFF INP 8-MSOP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD7450ABRM-REEL7

Rohs Status
RoHS non-compliant
Number Of Bits
12
Sampling Rate (per Second)
1M
Data Interface
DSP, MICROWIRE™, QSPI™, Serial, SPI™
Number Of Converters
1
Power Dissipation (max)
9.25mW
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
For Use With
EVAL-AD7450CBZ - BOARD EVALUATION FOR AD7450
MODES OF OPERATION
The operational mode of the AD7440/AD7450A is selected by
controlling the logic state of the CS signal during a conversion.
There are two possible modes of operation, normal and power-
down. The point at which
has been initiated determines whether or not the device enters
power-down mode. Similarly, if already in power-down, CS
controls whether the devices return to normal operation or
remain in power-down. These modes of operation are designed
to provide flexible power management options. These options
can be chosen to optimize the power dissipation/throughput
rate ratio for differing application requirements.
NORMAL MODE
This mode is intended for fastest throughput rate performance.
The user does not have to worry about any power-up times with
the AD7440/AD7450A remaining fully powered up all the time.
Figure 41 shows the general diagram of the operation of the
AD7440/AD7450A in this mode. The conversion is initiated on
the falling edge of CS , as described in the Serial Interface
section. To ensure the part remains fully powered up,
remain low until at least 10 SCLK falling edges have elapsed
after the falling edge of
If CS
but before the 16th SCLK falling edge, the part remains
powered up but the conversion terminates and SDATA goes
back into three-state. Sixteen serial clock cycles are required to
complete the conversion and access the complete conversion
result.
low until sometime prior to the next conversion. Once a data
transfer is complete, when SDATA has returned to three-state,
another conversion can be initiated after the quiet time, t
has elapsed by again bringing CS low.
SDATA
is brought high any time after the 10th SCLK falling edge,
SCLK
CS
CS
SDATA
SCLK
may idle high until the next conversion or may idle
CS
4 LEADING ZEROS + CONVERSION RESULT
1
Figure 41. Normal Mode Operation
A
1
PART BEGINS
TO POWER UP
CS .
CS is pulled high after the conversion
INVALID DATA
10
t
10
POWER-UP
16
Figure 43. Exiting Power-Down Mode
CS must
QUIET
Rev. C | Page 23 of 28
,
16
POWER-DOWN MODE
This mode is intended for use in applications where slower
throughput rates are required; either the ADC is powered down
between each conversion, or a series of conversions may be
performed at a high throughput rate and the ADC is then
powered down for a relatively long duration between these
bursts of conversions. When the AD7440/AD7450A are in the
power-down mode, all analog circuitry is powered down. To
enter power-down mode, the conversion process must be
interrupted by bringing
falling edge of SCLK and before the 10th falling edge of SCLK,
as shown in Figure 42.
Once
part enters power-down, the conversion that was initiated by
the falling edge of
three-state. The time from the rising edge of CS to SDATA
three-state enabled is never greater than t
Specifications). If CS is brought high before the second SCLK
falling edge, the part remains in normal mode and does not
power down. This avoids accidental power-down due to glitches
on the CS line.
In order to exit this mode of operation and power up the
AD7440/AD7450A again, a dummy conversion is performed.
On the falling edge of
continues to power up as long as CS is held low until after the
falling edge of the 10th SCLK. The device is fully powered up
after 1 μs has elapsed and, as shown in
results from the next conversion.
1
SDATA
SCLK
CS
CS
has been brought high in this window of SCLKs, the
THIS PART IS FULLY POWERED
UP WITH V
Figure 42. Entering Power-Down Mode
1
CS is terminated, and SDATA goes back into
2
CS , the device begins to power up and
IN
VALID DATA
CS high anywhere after the second
FULLY ACQUIRED
10
AD7440/AD7450A
THREE-STATE
Figure 43, valid data
8
10
(refer to the Timing
16

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