AD7450ABRMZ Analog Devices Inc, AD7450ABRMZ Datasheet

IC ADC 12BIT DIFF IN 1MSPS 8MSOP

AD7450ABRMZ

Manufacturer Part Number
AD7450ABRMZ
Description
IC ADC 12BIT DIFF IN 1MSPS 8MSOP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD7450ABRMZ

Data Interface
DSP, MICROWIRE™, QSPI™, Serial, SPI™
Number Of Bits
12
Sampling Rate (per Second)
1M
Number Of Converters
1
Power Dissipation (max)
9.25mW
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
Resolution (bits)
12bit
Sampling Rate
1MSPS
Input Channel Type
Differential
Supply Voltage Range - Analog
2.7V To 5.25V
Supply Current
1.95mA
Digital Ic Case Style
SOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-AD7450CBZ - BOARD EVALUATION FOR AD7450
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
FEATURES
Fast throughput rate: 1 MSPS
Specified for V
Low power at max throughput rate
Fully differential analog input
Wide input bandwidth
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface
Power-down mode: 1 μA max
8-lead SOT-23 and MSOP packages
APPLICATIONS
Transducer interface
Battery-powered systems
Data acquisition systems
Portable instrumentation
Motor control
GENERAL DESCRIPTION
The AD7440/AD7450A
power, successive approximation (SAR) analog-to-digital
converters with a fully differential analog input. These parts
operate from a single 3 V or 5 V power supply and use
advanced design techniques to achieve very low power
dissipation at throughput rates up to 1 MSPS. The SAR
architecture of these parts ensures that there are no pipeline
delays.
The parts contain a low noise, wide bandwidth, differential
track-and-hold amplifier (T/H) that can handle input
frequencies up to 3.5 MHz. The reference voltage is applied
externally to the V
3.5 V depending on the power supply and what suits the
application. The value of the reference voltage determines the
common-mode voltage range of the part. With this truly
differential input structure and variable reference input, the
user can select a variety of input ranges and bias points.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the device to interface
with microprocessors or DSPs. The input signals are sampled
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
4 mW max at 1 MSPS with 3 V supplies
9.25 mW max at 1 MSPS with 5 V supplies
70 dB SINAD at 100 kHz input frequency
SPI®/QSPI™/MICROWIRE™/DSP compatible
DD
of 3 V and 5 V
REF
pin and can be varied from 100 mV to
1
are 10-bit and 12-bit high speed, low
10-Bit and 12-Bit ADCs in an 8-Lead SOT-23
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
on the falling edge of CS ; the conversion is also initiated at this
point. The SAR architecture of these parts ensures that there are
no pipeline delays. The AD7440 and the AD7450A use ad-
vanced design techniques to achieve very low power dissipation
at high throughput rates.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
7.
8.
1
V
V
V
Protected by U.S. Patent Number 6,681,332.
REF
IN+
IN–
Operation with either 3 V or 5 V power supplies.
High throughput with low power consumption.
With a 3 V supply, the AD7440/AD7450A offer 4 mW
max power consumption for 1 MSPS throughput.
Fully differential analog input.
Flexible power/serial clock speed management.
The conversion rate is determined by the serial clock,
allowing the power to be reduced as the conversion time
is reduced through the serial clock speed increase. These
parts also feature a shutdown mode to maximize power
efficiency at lower throughput rates.
Variable voltage reference input.
No pipeline delay.
Accurate control of the sampling instant via a CS input and
once-off conversion control.
ENOB > eight bits typically with 100 mV reference.
AD7440/AD7450A
Differential Input, 1 MSPS
GND
FUNCTIONAL BLOCK DIAGRAM
V
DD
T/H
© 2005 Analog Devices, Inc. All rights reserved.
AD7440/AD7450A
APPROXIMATION
CONTROL LOGIC
Figure 1.
SUCCESSIVE
12-BIT
ADC
www.analog.com
SCLK
SDATA
CS

Related parts for AD7450ABRMZ

AD7450ABRMZ Summary of contents

Page 1

FEATURES Fast throughput rate: 1 MSPS Specified for and Low power at max throughput rate 4 mW max at 1 MSPS with 3 V supplies 9.25 mW max at 1 MSPS with 5 ...

Page 2

AD7440/AD7450A TABLE OF CONTENTS AD7440–Specifications.................................................................... 3 AD7450A–Specifications................................................................. 5 Timing Specifications....................................................................... 7 Absolute Maximum Ratings............................................................ 8 ESD Caution.................................................................................. 8 Pin Configurations and Function Descriptions ........................... 9 Terminology .................................................................................... 10 AD7440/AD7450A–Typical Performance Characteristics ....... 12 Circuit Information ........................................................................ 15 Converter Operation.................................................................. 15 ...

Page 3

AD7440–SPECIFICATIONS Table 2 3 MHz SCLK 2 REF CM REF A MIN Parameter DYNAMIC PERFORMANCE Signal-to-(Noise ...

Page 4

AD7440/AD7450A Parameter CONVERSION RATE Conversion Time 2 Track-and-Hold Acquisition Time Throughput Rate POWER REQUIREMENTS Normal Mode (Static) Normal Mode (Operational) Full Power-Down Mode Power Dissipation Normal Mode (Operational) Full Power-Down Mode 1 Common-mode voltage. The ...

Page 5

AD7450A–SPECIFICATIONS Table 2 3 MHz SCLK 2 REF CM REF A MIN Parameter DYNAMIC PERFORMANCE Signal-to-(Noise ...

Page 6

AD7440/AD7450A Parameter CONVERSION RATE Conversion Time 2 Track-and-Hold Acquisition Time Throughput Rate POWER REQUIREMENTS Normal Mode (Static) Normal Mode (Operational) Full Power-Down Mode Power Dissipation Normal Mode (Operational) Full Power-Down 1 Common-mode voltage. The input ...

Page 7

TIMING SPECIFICATIONS Guaranteed by characterization. All input signals are specified with (10 1.6 V. See Figure 2, Figure 3, and the Serial Interface section. Table 2.7 V ...

Page 8

AD7440/AD7450A ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 4. Parameter V to GND GND IN GND IN– Digital Input Voltage to GND Digital Output Voltage to GND V to GND REF ...

Page 9

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS AD7440/ SCLK 2 7 AD7450A SDATA 3 6 TOP VIEW CS (Not to Scale Figure 5. Pin Configuration for 8-Lead SOT-23 Table 5. Pin Function Descriptions Mnemonic Function V ...

Page 10

AD7440/AD7450A TERMINOLOGY Signal-to-(Noise + Distortion) Ratio This is the measured ratio of signal to (noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals ...

Page 11

Power Supply Rejection Ratio (PSRR) The power supply rejection ratio is the ratio of the power in the ADC output at full-scale frequency the power of a 100 mV p-p sine wave applied to the ADC V frequency ...

Page 12

AD7440/AD7450A AD7440/AD7450A–TYPICAL PERFORMANCE CHARACTERISTICS T = 25° MSPS MHz, unless otherwise noted SCLK 100 FREQUENCY (kHz) Figure 7. AD7450A SINAD vs. Analog Input Frequency ...

Page 13

POSITIVE DNL 0.5 0 –0.5 NEGATIVE DNL –1.0 0 0.5 1.0 1.5 2.0 2.5 V (V) REF Figure 13. Change in DNL vs. V for the AD7450A for V REF 2.5 2.0 1.5 1.0 POSITIVE ...

Page 14

AD7440/AD7450A 10,000 10,000 IN+ IN– CODES 10,000 CONVERSIONS 9,000 f = 1MSPS S 8,000 7,000 6,000 5,000 4,000 3,000 2,000 1,000 0 2044 2045 2046 2047 CODE Figure 19. Histogram of 10,000 Conversions Input ...

Page 15

CIRCUIT INFORMATION The AD7440/AD7450A are 10-bit and 12-bit fast, low power, single-supply, successive approximation analog-to-digital converters (ADCs). They can operate with power supply and are capable of throughput rates MSPS when ...

Page 16

AD7440/AD7450A TYPICAL CONNECTION DIAGRAM Figure 26 shows a typical connection diagram for the AD7440/AD7450A for both 5 V and 3 V supplies. In this setup, the GND pin is connected to the analog ground plane of the system. The V ...

Page 17

Figure 30 shows examples of the inputs to V different values of V for also gives the maximum REF DD and minimum common-mode voltages for each reference value according to Figure 28. REFERENCE = 2V ...

Page 18

AD7440/AD7450A DRIVING DIFFERENTIAL INPUTS Differential operation requires V and V IN+ simultaneously with two equal signals that are 180° out of phase. The common mode must be set up externally and has a range determined the power ...

Page 19

Op Amp Pair An op amp pair can be used to directly couple a differential signal to the AD7440/AD7450A. The circuit configurations shown in Figure 35 and Figure 36 show how a dual op amp can be used to convert ...

Page 20

AD7440/AD7450A Example 1 V max = max = REF REF then V max = 5 Therefore 3 × ...

Page 21

SERIAL INTERFACE Figure 2 and Figure 3 show detailed timing diagrams for the serial interface of the AD7450A and the AD7440, respectively. The serial clock provides the conversion clock and also controls the transfer of data from the devices during ...

Page 22

AD7440/AD7450A Timing Example 1 Having MHz and a throughput rate of 1 MSPS gives a SCLK cycle time of 1/Throughput = 1/1,000,000 = 1 μs A cycle consists 12.5(1 ...

Page 23

MODES OF OPERATION The operational mode of the AD7440/AD7450A is selected by controlling the logic state of the CS signal during a conversion. There are two possible modes of operation, normal and power pulled high after the conversion ...

Page 24

AD7440/AD7450A brought high before the 10th falling edge of SCLK, the AD7440/AD7450A again goes back into power-down. This avoids accidental power-up due to glitches on the CS line or an inadvertent burst of eight SCLK cycles while ...

Page 25

Thus, the average power dissipated during each cycle with a throughput rate of 100 kSPS is (2/10) × 0.8 mW. This is how the power numbers in Figure 44 are calculated. For throughput rates above 320 kSPS, ...

Page 26

AD7440/AD7450A AD7440/AD7450A to TMS320C5x/C54x The serial interface on the TMS320C5x/C54x uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices like the CS input allows easy interfacing AD7440/AD7450A. The between the TMS320C5x/C54x ...

Page 27

OUTLINE DIMENSIONS INDICATOR 0.15 MAX 2.90 BSC 1.60 BSC 2.80 BSC PIN 1 0.65 BSC 1.95 1.30 BSC 1.15 0.90 1.45 MAX 0.22 0.08 0.38 SEATING 0.22 PLANE COMPLIANT TO JEDEC STANDARDS ...

Page 28

... AD7450ABRT-R2 –40°C to +85°C 2 AD7450ABRTZ-REEL7 –40°C to +85°C AD7450ABRM –40°C to +85°C AD7450ABRM-REEL7 –40°C to +85°C 2 AD7450ABRMZ –40°C to +85°C 3 EVAL-AD7440CB 3 EVAL-AD7450ACB 4 EVAL-CONTROL BRD2 1 Linearity error here refers to integral nonlinearity error Pb-free part. ...

Related keywords