AD9649BCPZ-65 Analog Devices Inc, AD9649BCPZ-65 Datasheet
AD9649BCPZ-65
Specifications of AD9649BCPZ-65
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AD9649BCPZ-65 Summary of contents
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FEATURES 1.8 V analog supply operation 1 3.3 V output supply SNR 74.3 dBFS at 9.7 MHz input 71.5 dBFS at 200 MHz input SFDR 93 dBc at 9.7 MHz input 80 dBc at 200 MHz input Low ...
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AD9649 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications ..................................................................................... 4 DC Specifications ......................................................................... 4 AC Specifications .......................................................................... 5 Digital Specifications ...
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GENERAL DESCRIPTION The AD9649 is a monolithic, single channel 1.8 V supply, 14-bit, 20/40/65/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and an on-chip volt- age reference. The product uses multistage differential pipeline architecture with output ...
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AD9649 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted. Table 1. Parameter Temp RESOLUTION ...
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AC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted. Table 2. 1 Parameter SIGNAL-TO-NOISE RATIO (SNR) ...
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AD9649 DIGITAL SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted. Table 3. Parameter DIFFERENTIAL CLOCK INPUTS ...
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SWITCHING SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted. Table 4. Parameter CLOCK INPUT PARAMETERS Input ...
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AD9649 TIMING SPECIFICATIONS Table 5. Parameter Conditions SPI TIMING REQUIREMENTS t Setup time between the data and the rising edge of SCLK DS t Hold time between the data and the rising edge of SCLK DH t Period of the ...
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ABSOLUTE MAXIMUM RATINGS Table 6. Parameter 1 AVDD to AGND 1 DRVDD to AGND VIN+, VIN− to AGND 1 1 CLK+, CLK− to AGND 1 VREF to AGND 1 SENSE to AGND 1 VCM to AGND RBIAS to AGND 1 ...
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AD9649 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SDIO/PDWN NOTES 1. THE EXPOSED PADDLE MUST BE SOLDERED TO THE ANALOG GROUND Table 8. Pin Function Descriptions Pin No. Mnemonic Description 0 (EP) GND Exposed Paddle. The exposed paddle is the only ground ...
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TYPICAL PERFORMANCE CHARACTERISTICS AD9649-80 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted. 0 80MSPS 9.7MHz @ –1dBFS ...
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AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted. 100 SFDR (dBc SNR (dBFS) 60 ...
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AD9649 AD9649-65 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted. 0 65MSPS 9.7MHz @ –1dBFS –15 SNR ...
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AD9649-40 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted. 0 40MSPS 9.7MHz @ –1dBFS –15 SNR = ...
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AD9649-20 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted. 0 20MSPS 9.7MHz @ –1dBFS –15 SNR = ...
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AD9649 EQUIVALENT CIRCUITS AVDD VIN± Figure 27. Equivalent Analog Input Circuit AVDD VREF 7.5kΩ Figure 28. Equivalent VREF Circuit AVDD 375Ω SENSE Figure 29. Equivalent SENSE Circuit 5Ω CLK+ 15kΩ 15kΩ 5Ω CLK– Figure 30. Equivalent Clock Input Circuit 375Ω ...
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THEORY OF OPERATION The AD9649 architecture consists of a multistage, pipelined ADC. Each stage provides sufficient overlap to correct for flash errors in the preceding stage. The quantized outputs from each stage are combined into a final 14-bit result in ...
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AD9649 Differential Input Configurations Optimum performance is achieved while driving the AD9649 in a differential input configuration. For baseband applications, the AD8138, ADA4937-2, and ADA4938-2 provide excellent performance and a flexible interface to the ADC. The output common-mode voltage of ...
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VOLTAGE REFERENCE A stable and accurate 1.0 V voltage reference is built into the AD9649. The VREF can be configured using either the internal 1.0 V reference or an externally applied 1.0 V reference voltage. The various reference modes are ...
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AD9649 CLOCK INPUT CONSIDERATIONS For optimum performance, clock the AD9649 sample clock inputs, CLK+ and CLK−, with a differential signal. The signal is typi- cally ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are ...
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Clock Duty Cycle Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and result, may be sensitive to clock duty cycle. Commonly, a 50% duty cycle clock with ±5% tolerance is ...
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AD9649 Low power dissipation in power-down mode is achieved by shut- ting down the reference, reference buffer, biasing networks, and clock. Internal capacitors are discharged when entering power- down mode and then must be recharged when returning to normal operation. ...
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BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST The AD9649 includes a built-in test feature designed to enable verification of the integrity of each channel, as well as facilitate board-level debugging. Also included is a built-in self-test (BIST) feature that verifies the ...
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AD9649 SERIAL PORT INTERFACE (SPI) The AD9649 SPI allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on ...
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HARDWARE INTERFACE The pins described in Table 13 constitute the physical interface between the programming device of the user and the serial port of the AD9649. The SCLK pin and the CSB pin function as inputs when using the SPI ...
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AD9649 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Each row in the memory map register table (see Table 16) contains eight bit locations. The memory map is roughly divided into four sections: the chip configuration registers (Address 0x00 to ...
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MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 16 are not currently supported for this device. Table 16. Addr. (MSB) (Hex) Register Name Bit 7 Bit 6 Chip configuration registers 0x00 SPI port ...
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AD9649 Addr. (MSB) (Hex) Register Name Bit 7 Bit 6 0x14 Output mode 00 = 3.3 V CMOS 10 = 1.8 V CMOS 0x15 Output adjust 3.3 V DCO drive strength stripe (default stripes ...
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MEMORY MAP REGISTER DESCRIPTIONS For additional information about functions controlled in Register 0x00 to Register 0xFF, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. USR2 (Register 0x101) Bit 3—Enable GCLK Detect Normally set high, Bit 3 ...
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AD9649 APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting the design and layout of the AD9649 as a system recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain ...
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... SEATING PLANE ORDERING GUIDE Model Temperature Range 1, 2 AD9649BCPZ-80 –40°C to +85° AD9649BCPZRL7-80 –40°C to +85° AD9649BCPZ-65 –40°C to +85° AD9649BCPZRL7-65 –40°C to +85° AD9649BCPZ-40 –40°C to +85° AD9649BCPZRL7-40 –40°C to +85° AD9649BCPZ-20 –40°C to +85°C ...
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AD9649 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08539-0-10/09(0) Rev Page ...