KAD2710C-17Q68 Intersil, KAD2710C-17Q68 Datasheet

IC ADC 10BIT 170MSPS SGL 68-QFN

KAD2710C-17Q68

Manufacturer Part Number
KAD2710C-17Q68
Description
IC ADC 10BIT 170MSPS SGL 68-QFN
Manufacturer
Intersil
Series
FemtoCharge™r
Datasheet

Specifications of KAD2710C-17Q68

Number Of Bits
10
Sampling Rate (per Second)
170M
Data Interface
Parallel
Number Of Converters
1
Power Dissipation (max)
224mW
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
68-VQFN Exposed Pad, 68-HVQFN, 68-SQFN, 68-DHVQFN
For Use With
KDC2710CEVAL - DAUGHTER CARD FOR KAD2710
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
VREFSEL
10-Bit, 275/210/170/105MSPS A/D
Converter
The KAD2710C is the industry’s lowest power, 10-bit,
275MSPS, high performance Analog-to-Digital converter. It
is designed with Intersil’s proprietary FemtoCharge™
technology on a standard CMOS process. The KAD2710C
offers high dynamic performance (55.6dBFS SNR @
f
include an over-range indicator and a selectable divide-by-2
input clock divider. The KAD2710C is one member of a
pin-compatible family offering 8 and 10-bit ADCs with
sample rates from 105 to 350MSPS and LVDS-compatible or
LVCMOS outputs (Table 1). This family of products is
available in 68-pin RoHS-compliant QFN packages with
exposed paddle. Performance is specified over the full
industrial temperature range (-40°C to +85°C).
IN
CLK_N
CLK_P
VREF
VCM
INP
INN
= 138MHz) while consuming less than 265mW. Features
S/H
Generation
275MSPS
Clock
1.21V
®
10-bit
ADC
1
+
10
Data Sheet
LVCMOS
Drivers
1-888-INTERSIL or 1-888-468-3774
OR
CLKOUTP
CLKOUTN
D9 – D0
2SC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
FemtoCharge is a trademark of Kenet Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved
Features
• On-Chip Reference
• Internal Sample and Hold
• 1.5V
• 600MHz Analog Input Bandwidth
• Two’s Complement or Binary Output
• Over-Range Indicator
• Selectable ÷2 Clock Input
• LVCMOS Outputs
• Pb-Free (RoHS Compliant)
Applications
• High-Performance Data Acquisition
• Portable Oscilloscope
• Medical Imaging
• Cable Head Ends
• Power-Amplifier Linearization
• Radar and Satellite Antenna Array Processing
• Broadband Communications
• Point-to-Point Microwave Systems
• Communications Test Equipment
Key Specs
• SNR = 55.6dBFS at f
• SFDR = 68.5dBc at f
• Power consumption <265mW at f
Pin-Compatible Family
RESOLUTION, SPEED LVDS OUTPUTS LVCMOS OUTPUTS
10 Bits 275MSPS
10 Bits 210MSPS
10 Bits 170MSPS
10 Bits 105MSPS
December 5, 2008
8 Bits 350MSPS
8 Bits 275MSPS
8 Bits 210MSPS
8 Bits 170MSPS
8 Bits 105MSPS
P-P
All other trademarks mentioned are the property of their respective owners.
|
Differential Input Voltage
TABLE 1. PIN-COMPATIBLE PRODUCTS
Intersil (and design) is a registered trademark of Intersil Americas Inc.
S
S
= 275MSPS, f
KAD2708L-35
KAD2708L-27
KAD2708L-21
KAD2708L-17
KAD2708L-10
KAD2710L-27
KAD2710L-21
KAD2710L-17
KAD2710L-10
= 275MSPS, f
S
= 275MSPS
KAD2710C
IN
IN
= 138MHz
= 138MHz
KAD2708C-27
KAD2708C-21
KAD2708C-17
KAD2708C-10
KAD2710C-27
KAD2710C-21
KAD2710C-17
KAD2710C-10
FN6814.0

Related parts for KAD2710C-17Q68

KAD2710C-17Q68 Summary of contents

Page 1

... Features IN include an over-range indicator and a selectable divide-by-2 input clock divider. The KAD2710C is one member of a pin-compatible family offering 8 and 10-bit ADCs with sample rates from 105 to 350MSPS and LVDS-compatible or LVCMOS outputs (Table 1). This family of products is available in 68-pin RoHS-compliant QFN packages with exposed paddle ...

Page 2

... KAD2710C-27Q68 KAD2710C-21Q68 KAD2710C-17Q68 KAD2710C-10Q68 NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 ...

Page 3

... Functional Description ................................................. 12 Reset .......................................................................... 12 Voltage Reference...................................................... 12 Analog Input ............................................................... 12 Clock Input ................................................................. 13 Jitter............................................................................ 13 Digital Outputs ............................................................ 14 Equivalent Circuits........................................................ 14 Layout Considerations ................................................. 15 Split Ground and Power Planes ................................. 15 Clock Input Considerations......................................... 15 Bypass and Filtering ................................................... 15 LVCMOS Outputs....................................................... 15 Unused Inputs ............................................................ 15 Definitions...................................................................... 15 Package Outline Drawing ............................................. 16 L68.10x10B ..................................................................... 16 3 KAD2710C FN6814.0 December 5, 2008 ...

Page 4

... Nyquist 53.5 55.6 53.5 56.2 = 430MHz 55.2 = 10MHz 55.3 = Nyquist 52.5 55.2 52.5 56.0 = 430MHz 54.4 = 350MSPS, 270MSPS, SAMPLE KAD2710C-17 KAD2710C-10 1.5 1.6 1.4 1.5 1.6 1.4 1.5 210 198 178 860 860 860 1.8 1.9 1.7 1.8 1 ...

Page 5

... AVSS AVDD3 AVSS VIN = OVDD IH I VIN = OVSS CDI R CDI V CCI 350MSPS, 270MSPS, SAMPLE KAD2710C-17 KAD2710C-10 9.0 9.1 9.1 9.0 8.4 9.0 8.4 9.0 8.6 8 62.6 60.1 60 -12 -12 - 600 600 600 MIN TYP MAX 0.8*AVDD3 0.2*AVDD3 0 10 -90 -65 -30 0.8*AVDD3 ...

Page 6

... Industry-standard protection techniques have been utilized in the design of this product. However, reasonable care must be taken in the storage and handling of ESD sensitive products. Contact Intersil for the specific ESD sensitivity rating of this product. 6 KAD2710C Sample PID ...

Page 7

... Exposed Paddle 7 KAD2710C NAME AVDD2 1.8V Analog Supply AVSS Analog Supply Return VREF Reference Voltage Out/In VREFSEL Reference Voltage Select (0:Int 1:Ext) VCM Common-Mode Voltage Output AVDD3 3.3V Analog Supply INP, INN Analog Input Positive, Negative DNC Do Not Connect ...

Page 8

... VREF 3 VREFSEL 4 VCM 5 AVDD3 6 AVSS 7 INP 8 INN 9 AVSS 10 DNC 11 DNC 12 DNC 13 AVDD2 14 AVDD3 15 AVDD3 16 CLKDIV 17 8 KAD2710C KAD2710C (68 LD QFN) TOP VIEW KAD2710C 68 QFN Top View Not to Scale FIGURE 2. PIN CONFIGURATION DNC DNC DNC 45 OVSS 44 OVDD2 43 CLKOUT 42 DNC 41 OVDD2 DNC DNC ...

Page 9

... A (dBFS) IN FIGURE 5. SNR AND SFDR SFDR SNR 100 150 (MSPS) SAMPLE S FIGURE 7. SNR AND SFDR KAD2710C AVDD2 = OVDD2 = 1.8V, AVDD3 = 3.3V -0.5dBFS unless noted. IN -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 0 IN -40 -45 -50 -55 HD2 -60 -65 -70 -75 -80 -85 -90 -10 ...

Page 10

... CODE FIGURE 11. INTEGRAL NONLINEARITY vs OUTPUT CODE 0 -20 -40 -60 -80 -100 -120 FREQUENCY (MHz) FIGURE 13. OUTPUT SPECTRUM KAD2710C AVDD2 = OVDD2 = 1.8V, AVDD3 = 3.3V -0.5dBFS unless noted. (Continued 0.75 0.5 0.25 0 -0.25 -0.5 -0.75 200 250 300 -1 0 FIGURE 10. DIFFERENTIAL NONLINEARITY vs OUTPUT CODE ...

Page 11

... FREQUENCY (MHz) FIGURE 17. TWO-TONE SPECTRUM SFDR 65 60 SNR 55 50 -40 - Ambient Temperature deg.C FIGURE 19. SNR vs TEMPERATURE 11 KAD2710C AVDD2 = OVDD2 = 1.8V, AVDD3 = 3.3V -0.5dBFS unless noted. (Continued Ain = -0.50dBFS SNR = 56.0dBFS -20 SFD R = 63.6dBc -40 SINAD = 55.1dBc HD2 = -67.8dBc -60 HD3 = - 63.6dBc -80 -100 -120 0 80 ...

Page 12

... KAD2710C chips.One option in the latter configuration is to use one KAD2710C's internally generated reference as the external reference voltage for the other chips in the system. Additionally, an externally provided reference can be changed from the nominal value to adjust the full-scale input voltage within a limited range ...

Page 13

... AVDD2 0.1µF Clock Input KAD2710 Use of the clock divider is optional. The KAD2710C's ADC VCM requires a clock with 50% duty cycle for optimum 0.1µF performance. If such a clock is not available, one option is to generate twice the desired sampling rate and use the KAD2710C's divide-by-2 setting ...

Page 14

... No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 14 KAD2710C Digital Outputs Data is output on a parallel bus with LVCMOS drivers. The output format (Binary or Two’s Complement) is selected via the 2SC pin as shown in Table 3 ...

Page 15

... Differential Non-Linearity (DNL) is the deviation of any code width from an ideal 1 LSB step. 15 KAD2710C Effective Number of Bits (ENOB alternate method of specifying Signal to Noise-and-Distortion Ratio (SINAD calculated as: ENOB = (SINAD - 1.76)/6.02 Gain Error is the ratio of the difference between the voltages that cause the lowest and highest code transitions to the full-scale voltage (less 2 LSB) ...

Page 16

... Package Outline Drawing L68.10x10B 68 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 11/08 PIN 1 10.00 INDEX AREA 6 10.00 TOP VIEW 8.00 Sq 9.65 Sq 7.70 Sq TYPICAL RECOMMENDED LAND PATTERN 16 KAD2710C Exp. DAP 7.70 Sq. 35 (4X) 0.15 34 68X 0.55 BOTTOM VIEW 0.90 Max 64X 0.50 68X 0. ...

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