MAX1274BETC+ Maxim Integrated Products, MAX1274BETC+ Datasheet - Page 11

IC ADC 12BIT 1.8MSPS 12-TQFN

MAX1274BETC+

Manufacturer Part Number
MAX1274BETC+
Description
IC ADC 12BIT 1.8MSPS 12-TQFN
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of MAX1274BETC+

Number Of Bits
12
Sampling Rate (per Second)
1.8M
Data Interface
MICROWIRE™, QSPI™, Serial, SPI™
Number Of Converters
1
Power Dissipation (max)
45mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
12-WQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power consumption can be reduced significantly by plac-
ing the MAX1274/MAX1275 in either partial power-down
mode or full power-down mode. Partial power-down
mode is ideal for infrequent data sampling and fast wake-
up time applications. Pull CNVST high after the 3rd SCLK
rising edge and before the 14th SCLK rising edge to
enter and stay in partial power-down mode (see Figure
6). This reduces the supply current to 1mA. Drive CNVST
low and allow at least 14 SCLK cycles to elapse before
driving CNVST high to exit partial power-down mode.
Full power-down mode is ideal for infrequent data sam-
pling and very low supply current applications. The
MAX1274/MAX1275 have to be in partial power-down
mode in order to enter full power-down mode. Perform
the SCLK/CNVST sequence described above to enter
partial power-down mode. Then repeat the same
sequence to enter full power-down mode (see Figure
7). Drive CNVST low, and allow at least 14 SCLK cycles
to elapse before driving CNVST high to exit full power-
down mode. In partial/full power-down mode, maintain
a logic low or a logic high on SCLK to minimize power
consumption.
Figure 8 shows the unipolar transfer function for the
MAX1274. Figure 9 shows the bipolar transfer function for
the MAX1275. The MAX1274 output is straight binary,
while the MAX1275 output is two’s complement.
Figure 7. SPI Interface—Full Power-Down Mode
MODE
CNVST
DOUT
SCLK
______________________________________________________________________________________
1ST SCLK RISING EDGE
0
0
Partial Power-Down and
Full Power-Down Modes
0
NORMAL
1.8Msps, Single-Supply, Low-Power,
FIRST 8-BIT TRANSFER
D11
Transfer Function
D10
D9
True-Differential, 12-Bit ADCs
1ST SCLK RISING EDGE
D8
D7
PPD
An external reference is required for the MAX1274/
MAX1275. Use a 4.7µF and 0.01µF bypass capacitor on
the REF pin for best performance. The reference input
structure allows a voltage range of +1V to V
An analog-to-digital conversion is initiated by CNVST,
clocked by SCLK, and the resulting data is clocked out
on DOUT by SCLK. With SCLK idling high or low, a falling
edge on CNVST begins a conversion. This causes the
analog input stage to transition from track to hold mode,
and for DOUT to transition from high impedance to being
actively driven low. A total of 16 SCLK cycles are required
to complete a normal conversion. If CNVST is low during
the 16th falling SCLK edge, DOUT returns to high imped-
ance on the next rising edge of CNVST or SCLK,
enabling the serial interface to be shared by multiple
devices. If CNVST returns high after the 14th, but before
the 16th SCLK rising edge, DOUT remains active so con-
tinuous conversions can be sustained. The highest
throughput is achieved when performing continuous con-
versions. Figure 10 illustrates a conversion using a typical
serial interface.
0
DOUT ENTERS TRI-STATE ONCE CNVST GOES HIGH
0
EXECUTE PARTIAL POWER-DOWN TWICE
0
SECOND 8-BIT TRANSFER
Applications Information
RECOVERY
0
How to Start a Conversion
0
0
External Reference
0
0
DD
.
FPD
11

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