MAX1304ECM+T Maxim Integrated Products, MAX1304ECM+T Datasheet - Page 14

• Manufacturer Part Number: MAX1304ECM+T
• Description: IC ADC 12BIT 8CH 4MSPS 48LQFP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1304ECM+T

• Number Of Bits: 12
• Sampling Rate (per Second): 3.65M
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 1.82W
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
14
MAX1304
MAX1308
MAX1312
24, 39
25, 38
20
21
22
26
27
28
29
30
31
32
33
34
35
36
37
40
41
42
43
______________________________________________________________________________________
MAX1305
MAX1309
MAX1313
24, 39
25, 38
PIN
20
21
22
26
27
28
29
30
31
32
33
34
35
36
37
40
41
42
43
MAX1306
MAX1310
MAX1314
24, 39
25, 38
20
21
22
26
27
28
29
30
31
32
33
34
35
36
37
40
41
42
43
NAME
DGND
REF+
DV
COM
REF-
D10
D11
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DD
Positive Reference Bypass. Bypass REF+ with a 0.1µF capacitor to AGND.
Also bypass REF+ to REF- with a 2.2µF and a 0.1µF capacitor.
V
Reference Common Bypass. Bypass COM to AGND with a 2.2µF and a 0.1µF
capacitor. V
Negative Reference Bypass. Bypass REF- with a 0.1µF capacitor to AGND.
Also bypass REF- to REF+ with a 2.2µF and a 0.1µF capacitor.
V
Digital Ground. DGND is the power return for DV
pins together.
Digital Power Input. DV
including the parallel interface. Apply +2.7V to +5.25V to DV
DV
Digital I/O 0 of 12-Bit Parallel Data Bus. High impedance when
Digital I/O 1 of 12-Bit Parallel Data Bus. High impedance when
Digital I/O 2 of 12-Bit Parallel Data Bus. High impedance when
Digital I/O 3 of 12-Bit Parallel Data Bus. High impedance when
Digital I/O 4 of 12-Bit Parallel Data Bus. High impedance when
Digital I/O 5 of 12-Bit Parallel Data Bus. High impedance when
Digital I/O 6 of 12-Bit Parallel Data Bus. High impedance when
Digital I/O 7 of 12-Bit Parallel Data Bus. High impedance when
Digital Output 8 of 12-Bit Parallel Data Bus. High impedance when
Digital Output 9 of 12-Bit Parallel Data Bus. High impedance when
Digital Output 10 of 12-Bit Parallel Data Bus. High impedance when
or
Digital Output 11 of 12-Bit Parallel Data Bus. High impedance when
or
End-of-Conversion Output.
returns high on the next rising CLK edge or the falling CONVST edge.
End-of-Last-Conversion Output.
last conversion. It returns high when CONVST goes low for the next
conversion sequence.
Read Input. Pulling
Write Input. Pulling
device with D0–D7.
REF+
REF-
DD
= 1.
= 1.
= V
to DGND with a 0.1µF capacitor. Connect all DV
= 1.
= 1.
= V
COM
COM
COM
- V
+ V
= 13 / 25 x AV
REF
REF
/ 2.
low initiates a read command of the parallel data bus.
/ 2.
DD
low initiates a write command for configuring the
powers the digital section of the converter,
Pin Description (continued)
goes low to indicate the end of a conversion. It
DD
FUNCTION
.
goes low to indicate the end of the
DD
. Connect all DGND
DD
pins together.
DD
= 1 or
= 1 or
= 1 or
= 1 or
= 1 or
= 1 or
= 1 or
= 1 or
. Bypass
= 1 or
= 1 or
= 1
= 1
= 1.
= 1.
= 1.
= 1.
= 1.
= 1.
= 1.
= 1.