MAX1304ECM+T Maxim Integrated Products, MAX1304ECM+T Datasheet - Page 21

• Manufacturer Part Number: MAX1304ECM+T
• Description: IC ADC 12BIT 8CH 4MSPS 48LQFP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1304ECM+T

• Number Of Bits: 12
• Sampling Rate (per Second): 3.65M
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 1.82W
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
The bidirectional parallel digital interface allows for setting
the 8-bit configuration register (see the Configuration
Register section) and reading the 12-bit conversion
result. The interface includes the following control signals:
chip select (CS), read (RD), write (WR), end of conversion
(EOC), end of last conversion (EOLC), conversion start
(CONVST), shutdown (SHDN), channel shutdown
(CHSHDN), internal clock select (INTCLK/EXTCLK), and
external clock input (CLK). Figures 6, 7, 8, 9, Table 2, and
the Timing Characteristics show the operation of the inter-
face. D0–D7 are bidirectional, and D8–D11 are output
only. D0–D11 go high impedance when RD = 1 or CS = 1.
Enable channels as active by writing to the configura-
tion register through I/O lines D0–D7 (Table 2). The bits
in the configuration register map directly to the chan-
nels, with D0 controlling channel zero, and D7 control-
ling channel seven. Setting any bit high activates the
corresponding input channel, while resetting any bit
low deactivates the corresponding channel. On the
devices with less than eight channels, some of the bits
have no function (Table 2).
To write to the configuration register, pull CS and WR
low, load bits D0 through D7 onto the parallel bus, and
force WR high. The data are latched on the rising edge
of WR (Figure 6). Write to the configuration register at
any point during the conversion sequence. At power-
up, write to the configuration register to select the
active channels before beginning a conversion.
Table 2. Configuration Register
X = Don’t care (must be 1 or 0).
NUMBER
MAX1304
MAX1308
MAX1312
MAX1305
MAX1309
MAX1313
MAX1306
MAX1310
MAX1314
PART
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
Applications Information
STATE
______________________________________________________________________________________
OFF
OFF
OFF
ON
ON
ON
Configuration Register
D0/CH0
1
0
1
0
1
0
Digital Interface
D1/CH1
1
0
1
0
1
0
D2/CH2
X
X
1
0
1
0
However, the new configuration does not take effect
until the next CONVST falling edge. At power-up all
channels default active. Shutdown does not change the
configuration register. The configuration register may
be written to in shutdown. See the Channel Shutdown
( CHSHDN ) section for information about using the con-
figuration register for power saving.
Figure 6. Write Timing
D3/CH3
CONVST
D0–D7
BIT/CHANNEL
X
X
1
0
1
0
WR
RD
CS
t
D4/CH4
CTW
X
X
X
X
1
0
D5/CH5
REGISTER UPDATES
t
DTW
1
0
X
X
X
X
CONFIGURATION
t
WRL
t
CS
DATA-IN
D6/CH6
X
X
X
X
1
0
t
D7/CH7
t
WTC
WTD
1
0
X
X
X
X
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