MAX1304ECM+T Maxim Integrated Products, MAX1304ECM+T Datasheet - Page 23

IC ADC 12BIT 8CH 4MSPS 48LQFP

MAX1304ECM+T

Manufacturer Part Number
MAX1304ECM+T
Description
IC ADC 12BIT 8CH 4MSPS 48LQFP
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of MAX1304ECM+T

Number Of Bits
12
Sampling Rate (per Second)
3.65M
Data Interface
Parallel
Number Of Converters
1
Power Dissipation (max)
1.82W
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
Figure 8. Read During Conversion—Channel 3 and Channel 7 Selected, External Clock
Figures 7 and 8 show the interface signals to initiate a
read operation during a conversion cycle. These figures
show two channels selected for conversion. If more
channels are selected, the results are available succes-
sively at every EOC falling edge. CS can be low at all
times, low during the RD cycles, or the same as RD.
After initiating a conversion by bringing CONVST high,
wait for EOC to go low. In internal clock mode, EOC
goes low within 900ns. In external clock mode, EOC
goes low on the rising edge of the 13th CLK cycle. To
read the conversion result, drive CS and RD low to
latch data to the parallel digital output bus. Bring RD
CONVST
D0–D11
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
EOLC
EOC
CLK
CS*
RD
*CS CAN BE LOW AT ALL TIMES, LOW DURING THE RD CYCLES, OR THE SAME AS RD.
TRACK
t
t
ACQ
CNTC
______________________________________________________________________________________
Reading a Conversion Result
SAMPLE
INSTANT
Reading During a Conversion
1
2
t
CONV
3
t
EOCD
12
t
CTR
t
CLK
t
ACC
HOLD
13
t
REQ
t
EOC
CH3
high to release the digital bus. In internal clock mode,
the next EOC falling edge occurs within 225ns. In exter-
nal clock mode, the next EOC falling edge occurs in
three CLK cycles. When the last result is available
EOLC goes low.
Figure 9 shows the interface signals for a read operation
after a conversion with all eight channels enabled. At
the falling of EOLC, driving CS and RD low places the
first conversion result onto the parallel bus. Successive
low pulses of RD place the successive conversion
results onto the bus. When the last conversion results in
the sequence are read, additional read pulses wrap the
pointer back to the first converted result.
14
t
NEXT
t
RDH
t
CLKH
15
t
RDL
16
t
CLKL
t
CH7
EOLCD
t
17
QUIET
t
RTC
Reading After Conversion
t
≥ 50ns
EOCD
18
TRACK
t
CVEOLCD
19
1
23

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