AD1871YRS Analog Devices Inc, AD1871YRS Datasheet
AD1871YRS
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AD1871YRS Summary of contents
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FEATURES 5.0 V Stereo Audio ADC with 3.3 V Tolerant Digital Interface Supports 96 kHz Sample Rates Supports 16-/20-/24-Bit Word Lengths Multibit Sigma-Delta Modulators with “Perfect Differential Linearity Restoration” for Reduced Idle Tones and Noise Floor 105 dB (Typ) ...
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AD1871 TABLE OF CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AD1871–SPECIFICATIONS TEST CONDITIONS UNLESS OTHERWISE NOTED Supply Voltages . . . . . . . . . . . . . . . . . . . . . . 5.0 V Ambient Temperature . . . . . . ...
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AD1871–SPECIFICATIONS LOW-PASS DIGITAL FILTER CHARACTERISTICS (f Parameter Decimation Factor Pass-Band Frequency Stop-Band Frequency Pass-Band Ripple Stop-Band Attenuation Group Delay LOW-PASS DIGITAL FILTER CHARACTERISTICS (f Parameter Decimation Factor Pass-Band Frequency Stop-Band Frequency Pass-Band Ripple Stop-Band Attenuation Group Delay HIGH-PASS DIGITAL FILTER ...
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DATA INTERFACE TIMING (STANDALONE MODE–MASTER) Mnemonic Description t BCLK Delay BDLY t LRCLK Delay to Low BLDLY t DOUT Delay BDDLY MCLK t BDLY BCLK t BLDLY LRCLK t BDDLY DOUT LEFT-JUSTIFIED MSB MODE DOUT 2 I S-JUSTIFIED MODE DOUT ...
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AD1871 DATA INTERFACE TIMING (STANDALONE MODE–SLAVE) Mnemonic Description t BCLK High Width BCH t BCLK Low Width BCL t DOUT Delay BDSD t LRCLK Setup LRS t LRCLK Hold LRH t BCH BCLK t LRS LRCLK t BDSD DOUT LEFT-JUSTIFIED ...
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DATA INTERFACE TIMING (CASCADE MODE–MASTER) Mnemonic Description t BCLK High Delay BCHDC t BCLK Low Delay BCLDC t LRCLK Delay BLRDC t DOUT Delay BDDC t DIN Setup BDIS t DIN Hold BDIH DATA INTERFACE TIMING (CASCADE MODE–SLAVE) Mnemonic Description ...
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AD1871 CONTROL INTERFACE (SPI) TIMING Mnemonic Description t CCLK High Width CCH t CCLK Low Width CCL t CCLK Period CCP t CDATA Setup Time CDS t CDATA Hold Time CDH t CLATCH Setup Time CLS t CLATCH Hold Time ...
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... Reference Voltage Soldering (10 sec) Model Temperature AD1871YRS –40∞C to +105∞C AD1871YRS-REEL –40∞C to +105∞C EVAL-AD1871EB CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1871 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges ...
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AD1871 Pin Input/ No. Output Mnemonic 1 I MCLK CCLK I/O COUT CIN CLATCH 6 I DVDD 7 I DGND 8 I XCTRL 9 I AVDD 10 I ...
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Pin Function Redefinition in External Control Mode Pin Input/ No. Output Mnemonic 256/512 DF0 4 I DF1 M Pin Function Redefinition in Modulator Mode Pin Input/ No. Output Mnemonic 3 O MODCLK 25 O ...
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AD1871 TERMINOLOGY Dynamic Range The ratio of a full-scale input signal to the integrated input noise in the pass band ( kHz), expressed in decibels (dB). Dynamic range is measured with a –60 dB input signal and ...
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FILTER RESPONSES 0 –20 –40 –60 –80 –100 –120 –140 –160 0 5 FREQUENCY – NORMALIZED TO TPC 1. Sinc Filter Response (AMC = 0) 0 –20 –40 –60 –80 –100 –120 –140 –160 0 5 FREQUENCY – NORMALIZED TO ...
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AD1871 DEVICE PERFORMANCE CURVES 5 0 –5 –10 –15 –20 –25 – FREQUENCY – Hz TPC 7. High-Pass Filter Response –5 –10 –15 –20 –25 – FREQUENCY – Hz TPC 8. ...
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TPC 13. THD+N vs. Input Frequency at –0.5 dBFS, f –90 –95 –100 –105 –110 –115 –120 kHz TPC 14. Channel ...
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AD1871 FUNCTIONAL DESCRIPTION Clocking Scheme The MCLK pin is the input for the master clock frequency to the device. Nominally the MCLK frequency will be 256 ¥ f correct operation of the device. However, if the user’s MCLK is a ...
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Digital Decimating Filters The filtering and decimation of the AD1871’s modulator data stream is implemented in an embedded DSP engine. The first stage of filtering is the sinc filtering, which has selectable deci- mation (selected by the modulator clock control ...
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AD1871 Mode Mode, the data is left-justified, MSB first, with the MSB placed in the second BCLK period following the transition of the LRCLK. A high-to-low transition of the LRCLK signifies LRCLK BCLK ...
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Cascade Mode The AD1871 supports cascading four devices in a daisy-chain configuration to the serial port of a DSP. In Cascade Mode, each device loads an internal 64-Bit Shift Register with the results of the left and ...
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AD1871 LRCLK BCLK DOU T DEV BCLK DOU LSB M SB LSB – 1 – LEFT CLAT CH CCLK ...
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Address R/W Reserved CCLK CLATCH CIN D15 COUT CCLK CLATCH D15 CIN COUT Figure 21. Reading from Register Using Control Port Table IV. Control Register I (Address 0000b, Write Only) 15– 0000 0 0 ...
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AD1871 Modulator Clock The modulator clock can be chosen to be either 128 ¥ ¥ The AMC Bit (Bit 6) is used to select the modulator’s S clock rate. When AMC is set to 0 (default), ...
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Reserved 7–6 MCD1–MCD0 Master Clock Divider (See Table XIII) 5 SEL 4 SER 3 MEL 2 MXL 1 MER 0 MXR Control Register III Control Register III contains bit settings for configuration ...
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AD1871 Table XIV. Peak Reading Register I (Address 0011b, Read-Only) 15– 0011 1 0 9–6 Reserved 5–0 A0P5–A0P0 Table XV. Peak Reading Register II (Address 0100b, Read-Only) 15– 0100 1 0 9–6 Reserved 5–0 ...
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INTERFACING Analog Interfacing The analog section of the AD1871 has been designed to offer flexibility as well as high performance. Users may choose full differential input directly to the ADC’s - modulator via Pins CAPxP and CAPxN. Alternatively, when using ...
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AD1871 LAYOUT CONSIDERATIONS In order to operate the AD1871 at its specified performance level, careful consideration must be given to the layout of the AD1871 and its ancillary circuits. Since the analog inputs to the AD1871 are differential, the voltages ...
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PIN 1 2.00 MAX 0.05 MIN REV. 0 OUTLINE DIMENSIONS 28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters 10.50 10.20 9. 5.60 8.20 5.30 7.80 5.00 7. 1.85 1.75 0.10 1.65 COPLANARITY 0.25 ...
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