AD6644AST-65 Analog Devices Inc, AD6644AST-65 Datasheet

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AD6644AST-65

Manufacturer Part Number
AD6644AST-65
Description
IC ADC 14BIT 65MSPS CMOS 52-LQFP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD6644AST-65

Rohs Status
RoHS non-compliant
Number Of Bits
14
Sampling Rate (per Second)
65M
Data Interface
Parallel
Number Of Converters
4
Power Dissipation (max)
1.3W
Voltage Supply Source
Analog and Digital
Operating Temperature
-25°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
52-LQFP

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FEATURES
65 MSPS guaranteed sample rate
40 MSPS version available
Sampling jitter < 300 fs
100 dB multitone SFDR
1.3 W power dissipation
Differential analog inputs
Pin compatible to AD6645
Twos complement digital output format
3.3 V CMOS compatible
Data-ready for output latching
APPLICATIONS
Multichannel, multimode receivers
AMPS, IS-136, CDMA, GSM, WCDMA
Single channel digital receivers
Antenna array processing
Communications instrumentation
Radar, infrared imaging
Instrumentation
GENERAL DESCRIPTION
The AD6644 is a high speed, high performance, monolithic 14-bit
analog-to-digital converter (ADC). All necessary functions,
including track-and-hold (TH) and reference, are included on-
chip to provide a complete conversion solution. The AD6644
provides CMOS-compatible digital outputs. It is the third
generation in a wideband ADC family, preceded by the AD9042
(12-bit 41 MSPS) and the AD6640 (12-bit 65 MSPS, IF
sampling).
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
ENCODE
ENCODE
V
AIN
AIN
REF
A1
INTERNAL
2.4V
AV
TIMING
GND
CC
TH1
DV
CC
DMID OVR DRY D13
ADC1
FUNCTIONAL BLOCK DIAGRAM
TH2
5
DAC1
(MSB)
D12 D11 D10 D9
DIGITAL ERROR CORRECTION LOGIC
A2
Figure 1.
TH3
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
Designed for multichannel, multimode receivers, the AD6644
is part of the Analog Devices, Inc. new SoftCell® transceiver
chipset. The AD6644 achieves 100 dB multitone, spurious-free
dynamic range (SFDR) through the Nyquist band. This break-
through performance eases the burden placed on multimode
digital receivers (software radios) which are typically limited by
the ADC. Noise performance is exceptional; typical signal-to-
noise ratio is 74 dB.
The AD6644 is also useful in single channel digital receivers
designed for use in wide-channel bandwidth systems (CDMA,
WCDMA). With oversampling, harmonics can be placed
outside the analysis bandwidth. Oversampling also facilitates
the use of decimation receivers (such as the AD6620), allowing
the noise floor in the analysis bandwidth to be reduced. By
replacing traditional analog filters with predictable digital
components, modern receivers can be built using fewer RF
components, resulting in decreased manufacturing costs, higher
manufacturing yields, and improved reliability.
The AD6644 is built on the Analog Devices high speed
complementary bipolar process (XFCB) and uses an innovative,
multipass circuit architecture. Units are packaged in a 52-lead
plastic low profile quad flat package (LQFP) specified from –
25°C to +85°C.
PRODUCT HIGHLIGHTS
1. Guaranteed sample rate is 65 MSPS.
2. Fully differential analog input stage.
3. Digital outputs can be run on 3.3 V supply for easy interface
4. Complete solution: reference and track-and-hold.
5. Packaged in small, surface-mount, plastic, 52-lead LQFP.
D8
to digital ASICs.
ADC2
TH4
Analog-to-Digital Converter
D7
5
14-Bit, 40 MSPS/65 MSPS
D6
DAC2
D5
D4
TH5
D3
AD6644
©2007 Analog Devices, Inc. All rights reserved.
D2
ADC3
D1
(LSB)
D0
6
AD6644
www.analog.com

Related parts for AD6644AST-65

AD6644AST-65 Summary of contents

Page 1

FEATURES 65 MSPS guaranteed sample rate 40 MSPS version available Sampling jitter < 300 fs 100 dB multitone SFDR 1.3 W power dissipation Differential analog inputs Pin compatible to AD6645 Twos complement digital output format 3.3 V CMOS compatible Data-ready ...

Page 2

AD6644 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 DC Specifications ......................................................................... 3 Digital Specifications ................................................................... 4 Switching Specifications .............................................................. 4 ...

Page 3

... Full V 2.2 Full V 25°C V 1.5 Full II 4.85 5.0 Full II 3.0 3.3 Full II 245 Full II 30 Full IV Full II 1.3 Rev Page AD6644AST-65 Max Min Typ 14 Guaranteed +10 −10 +3 +10 −10 –6 +1.5 −1.0 ±0.25 ±0. ±1.0 2.4 2 1.5 5.25 4.85 5.0 3.6 3 ...

Page 4

... Min Typ 0 2.5 2.5 CMOS CMOS 2.5 2.5 0.4 0.4 Twos complement –25° +85°C, unless otherwise noted. MIN MAX AD6644AST-65 Typ Max Min Typ Max 6.5 6.5 = −25° +85°C, C MIN MAX LOAD AD6644AST-40/65 1 Min Typ 15.4 25 6.2 7.7 6.2 7 ...

Page 5

... To calculate t ENC −9 −9 + 8.6 × 13.4 × −9 −9 = 10.3 × −25° +85°C, unless otherwise noted. MIN MAX AD6644AST-40 AD6644AST-65 1 Min Typ Max Min Typ 74.5 74.5 74.0 72 74.0 73.5 72 73.5 74.5 74.5 74 ...

Page 6

AD6644 TIMING DIAGRAM AIN ENCODE, ENCODE t E_RL D[13:0], OVR DRY ENCH ENCL t ENC E_FL E_DR N – 3 ...

Page 7

ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Electrical AV Voltage CC DV Voltage CC Analog Input Voltage Analog Input Current Digital Input Voltage Digital Output Current Environmental Operating Temperature Range (Ambient) Storage Temperature Range (Ambient) Lead Temperature (Soldering, 10 sec) Maximum ...

Page 8

AD6644 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DNC = DO NOT CONNECT Table 8. Pin Function Descriptions Pin Number 1, 33 10, 13, 15, 17, 19, 21, 23, 25, 27, 29, 34 ...

Page 9

TYPICAL PERFORMANCE CHARACTERISTICS 0 ENCODE = 65MSPS –10 AIN = 2.2MHz @ –1dBFS SNR = 74.5dB –20 SFDR = 92dBc –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 FREQUENCY (MHz) Figure 4. ...

Page 10

AD6644 100 ENCODE = 65MSPS 95 WORST OTHER SPUR AIN = –1dBFS HARMONICS (SECOND, THIRD ANALOG FREQUENCY (MHz) Figure 10. Harmonics vs. Analog Frequency (IF) ...

Page 11

ENCODE = 65MSPS –10 AIN = 15.5MHz @ –29.5dBFS NO DITHER –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 FREQUENCY (MHz) Figure 16. 1M FFT Without Dither 100 ENCODE ...

Page 12

AD6644 EQUIVALENT CIRCUITS AIN BUF 500Ω BUF 500Ω AIN BUF V CL Figure 21. Analog Input Stage LOADS 10kΩ ENCODE 10kΩ LOADS Figure 22. ENCODE/ ENCODE ...

Page 13

TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point of the rising edge of ...

Page 14

AD6644 Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. Reported in either dBc (that is, degrades ...

Page 15

THEORY OF OPERATION The AD6644 analog-to-digital converter (ADC) employs a three-stage subrange architecture. This design approach achieves the required accuracy and speed while maintaining low power and small die size. As shown in the functional block diagram, the AD6644 has ...

Page 16

AD6644 input matches Ω source with a full-scale drive of 4.8 dBm. Series resistors ( the secondary side of the S transformer should be used to isolate the transformer from the ADC. This limits the ...

Page 17

Jitter Considerations The signal-to-noise ratio (SNR) for an ADC can be predicted. When normalized to ADC codes, Equation 1 accurately predicts the SNR based on three terms. These are jitter, average DNL error, and thermal noise. Each of these terms ...

Page 18

AD6644 EVALUATION BOARD The schematic of the evaluation board (see Figure 32) repre- sents a typical implementation of the AD6644. A multilayer board is recommended to achieve best results highly recommended that high quality, ceramic chip capacitors be ...

Page 19

D4 C AVC +3P3V C DVC AVC D10 C AVC D11 D GN D12 C AVC D13 ...

Page 20

AD6644 Figure 33. Top Signal Level Figure 34. 5.0 V Plane Layer 3 and 3.3 V Plane Layer 4 Figure 35. Ground Plane Layer 2 and Ground Plane Layer 5 Figure 36. Bottom Signal Layer Rev Page 20 ...

Page 21

... SEATING 0.05 PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range AD6644AST-40 −25°C to +85°C 1 AD6644ASTZ-40 −25°C to +85°C AD6644AST-65 −25°C to +85°C 1 AD6644ASTZ-65 −25°C to +85°C AD6644ST/PCB 1 AD6644ST/PCBZ RoHS Compliant Part. 12.20 12.00 SQ 0.75 11.80 1 ...

Page 22

AD6644 NOTES Rev Page ...

Page 23

NOTES Rev Page AD6644 ...

Page 24

AD6644 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00971-0-8/07(D) Rev Page ...

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