AD9054ABST-200 Analog Devices Inc, AD9054ABST-200 Datasheet

IC ADC 8BIT 200MSPS 44-LQFP

AD9054ABST-200

Manufacturer Part Number
AD9054ABST-200
Description
IC ADC 8BIT 200MSPS 44-LQFP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9054ABST-200

Rohs Status
RoHS non-compliant
Number Of Bits
8
Sampling Rate (per Second)
200M
Data Interface
Parallel
Number Of Converters
1
Power Dissipation (max)
781mW
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
44-LQFP

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GENERAL DESCRIPTION
The AD9054A is an 8-bit monolithic analog-to-digital converter
optimized for high speed, low power, small size and ease of use.
With a 200 MSPS encode rate capability and full-power analog
bandwidth of 350 MHz, the component is ideal for applications
requiring the highest possible dynamic performance.
To minimize system cost and power dissipation, the AD9054A
includes an internal 2.5 V reference and track-and-hold circuit.
The user provides only a 5 V power supply and an encode clock.
No external reference or driver components are required for
many applications.
The AD9054A’s encode input interfaces directly to TTL, CMOS
or positive-ECL logic and will operate with single-ended or
differential inputs. The user may select dual-channel or single-
channel digital outputs. The dual (demultiplexed) mode inter-
leaves ADC data through two 8-bit channels at one-half the
clock rate. Operation in demultiplexed mode reduces the speed
and cost of external digital interfaces while allowing the ADC to
be clocked to the full 200 MSPS conversion rate. In the single-
channel (nondemultiplexed) mode, all data is piped at the full
clock rate to the Channel A outputs.
Fabricated with an advanced BiCMOS process, the AD9054A is
provided in a space-saving 44-lead LQFP surface mount plastic
package (ST-44) and specified over the full industrial (–40°C to
+85°C) temperature range.
ENCODE
ENCODE
AIN
AIN
FUNCTIONAL BLOCK DIAGRAM
V
AD9054A
TIMING
DD
T/H
GND
QUANTIZER
VREF IN
DEMUX
8-Bit, 200 MSPS
A/D Converter
2.5V REFERENCE
DEMULTIPLEXER
VREF OUT
DS
ENCODE
LOGIC
AD9054A
DS
8
8
DA
DB
7
7
–DA
–DB
0
0

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AD9054ABST-200 Summary of contents

Page 1

GENERAL DESCRIPTION The AD9054A is an 8-bit monolithic analog-to-digital converter optimized for high speed, low power, small size and ease of use. With a 200 MSPS encode rate capability and full-power analog bandwidth of 350 MHz, the component is ...

Page 2

... ICM DEMUX INPUT HIGH Input Voltage ( LOW Input Voltage ( DIGITAL OUTPUTS HIGH Output Voltage ( LOW Output Voltage ( Output Coding ( external reference Test AD9054ABST-200 Temp Level Min Typ 8 ± 0.9 25°C I ± 1.0 Full VI ± 0.6 25°C I ± 0.9 Full VI Full VI Guaranteed ± ...

Page 3

... SNR/harmonics based on an analog input voltage of –1.0 dBFS referenced to a 1.024 V full-scale input range. Specifications subject to change without notice. EXPLANATION OF TEST LEVELS Test Level I. 100% production tested. II. 100% production tested at 25°C and sample tested at speci- fied temperatures. III. Sample tested only. Test AD9054ABST-200 Temp Level Min Typ Full VI 128 Full ...

Page 4

... Exposure to absolute maximum ratings for extended periods may affect device reliability. ORDERING GUIDE Temperature Model Range AD9054ABST-200 –40°C to +85°C AD9054ABST-135 –40°C to +85°C AD9054A/PCB 25° Plastic Thin Quad Flatpack (LQFP). ...

Page 5

PIN FUNCTION DESCRIPTIONS Pin Number Mnemonic Function 1 ENCODE Encode Clock for ADC (ADC Samples on Rising Edge of ENCODE) ENCODE 2 Encode Clock Complement (ADC Samples on Falling Edge of ENCODE 15, 18, 28, VDD Power Supply ...

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AD9054A SAMPLE N–1 AIN SAMPLE N– ENCODE ENCODE t HDS t HDS t SDS PWDS PORT A DATA N–7 DATA N–7 D –D OR N– PORT B DATA N–8 DATA N–6 ...

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EQUIVALENT CIRCUITS AIN V DD VREF IN 300 ENCODE AIN V DD 17.5k 300 ENCODE OR DS 7.5k AD9054A 17.5k 300 300 DEMUX 7.5k DEMUX V DD DIGITAL OUTPUTS V DD VREF OUT V DD ...

Page 8

AD9054A–Typical Performance Characteristics 55 50 SNR 45 SINAD 40 NYQUIST FREQUENCY 35 (100MHz – MHz SNR 45 44 SINAD 100 ...

Page 9

10.3MHz SNR SINAD 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 ENCODE PULSEWIDTH – 70MHz 42 ...

Page 10

AD9054A –40 –45 –50 70MHz –55 50MHz –60 20MHz –65 –70 –60 –40 – – –40 –45 –50 70MHz –55 –60 –65 –70 –60 –40 – – –40 ...

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F1 = 55.0MHz – 56.0MHz –7.0dBFS –20 –30 –40 –50 –60 –70 –80 –90 –100 MHz 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 ...

Page 12

AD9054A 2.502 2.501 2.500 2.499 2.498 –40 – – C AMB APPLICATION NOTES THEORY OF OPERATION The AD9054A combines Analog Devices’ patented MagAmp bit-per-stage architecture with flash converter technology to create a high performance, low power ...

Page 13

Digital Inputs SNR performance is directly related to the sampling clock sta- bility in A/D converters, particularly for high input frequencies and wide bandwidths. A low jitter clock (< 100 MHz) is essential for optimum performance when digitizing ...

Page 14

AD9054A Applications that call for the AD9054A to be synchronized at power-up or only periodically during calibration/reset (i.e., valid data is not required prior to synchronization), need only be concerned with the timing of the falling edge of DS. The ...

Page 15

EVALUATION BOARD The AD9054A evaluation board offers an easy way to test the AD9054A. It provides dc biasing for the analog input, generates the latch clocks for both full speed and demuxed modes, and includes a reconstruction DAC. The board ...

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AD9054A ...

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AD9054A ...

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... MC74F574DW 23 1 AD9631AR 24 1 AD9760AR 25 1 AD9054ABST 26 1 P8002SCT- 90F1533 PARTS NOT ON BILL OF MATERIALS, AND NOT TO BE INSTALLED: C5, C36, C37, R17–R20. BILL OF MATERIALS REFERENCE DESCRIPTION 0.1 µF CER CHIP CAP 0805 C1, C2, C4, C6–C8, C10–C22, C24–C29, C31– ...

Page 19

OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 44-Lead Plastic Thin Quad Flatpack (LQFP) (ST-44) 0.063 (1.60) MAX 0.472 (12.00) BSC SQ 0.030 (0.75) 33 0.018 (0.45) 34 SEATING PLANE TOP VIEW (PINS DOWN 0.006 (0.15) 0.002 ...

Page 20

AD9054A –Revision History Location Data Sheet changed from REV REV. D. Edit to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . ...

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