AD9640BCPZ-125 Analog Devices Inc, AD9640BCPZ-125 Datasheet
AD9640BCPZ-125
Specifications of AD9640BCPZ-125
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AD9640BCPZ-125 Summary of contents
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FEATURES SNR = 71.8 dBc (72.8 dBFS MHz @ 125 MSPS SFDR = 85 dBc to 70 MHz @ 125 MSPS Low power: 750 mW @ 125 MSPS SNR = 71.6 dBc (72.6 dBFS MHz @ ...
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... ADC AC Specifications—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, and AD9640BCPZ 150 ......................................................................... 8 Digital Specifications ................................................................... 9 Switching Specifications—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, and AD9640BCPZ-105 ..................................................................... 10 Switching Specifications—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, and AD9640BCPZ-150 ..................................................................... 11 Timing Specifications ................................................................ 12 Absolute Maximum Ratings .......................................................... 14 Thermal Characteristics ............................................................ 14 ESD Caution ................................................................................ 14 Pin Configurations and Function Descriptions ......................... 15 Equivalent Circuits ......................................................................... 19 Typical Performance Characteristics ........................................... 20 Theory of Operation ...
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REVISION HISTORY 12/09—Rev Rev. B Added CP-64-6 Package .................................................... Universal Changes to Ordering Guide ........................................................... 51 6/09—Rev Rev. A Changes to Applications Section and Product Highlights Section ............................................................................. 1 Changes to General Description Section ....................................... 3 ...
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AD9640 GENERAL DESCRIPTION The AD9640 is a dual 14-bit, 80/105/125/150 MSPS analog-to- digital converter (ADC). The AD9640 is designed to support communications applications where low cost, small size, and versatility are desired. The dual ADC core features a multistage, differential ...
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... SPECIFICATIONS ADC DC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, AND AD9640BCPZ-105 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect outputs disabled, and signal monitor disabled, unless otherwise noted. Table 1. Parameter RESOLUTION ...
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... AD9640 ADC DC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, AND AD9640BCPZ-150 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect outputs disabled, and signal monitor disabled, unless otherwise noted. Table 2. Parameter RESOLUTION ...
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... ADC AC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, AND AD9640BCPZ-105 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect outputs disabled, and signal monitor disabled, unless otherwise noted. Table 3. 1 Parameter SIGNAL-TO-NOISE RATIO (SNR ...
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... AD9640 ADC AC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, AND AD9640BCPZ 150 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect outputs disabled, and signal monitor disabled, unless otherwise noted. Table 4. 1 Parameter ...
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DIGITAL SPECIFICATIONS AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 5. Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, ...
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... Reduced Swing Mode OS 1 Pull up. 2 Pull down. SWITCHING SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, AND AD9640BCPZ-105 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 6. Parameter CLOCK INPUT PARAMETERS ...
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... Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load. 3 Wake-up time is dependent on the value of the decoupling capacitors. SWITCHING SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, AND AD9640BCPZ-150 AVDD = 1.8 V, DVDD = 1.8V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted ...
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AD9640 TIMING SPECIFICATIONS Table 8. Parameter Conditions SYNC TIMING REQUIREMENTS t SYNC to rising edge of CLK setup time SSYNC t SYNC to rising edge of CLK hold time HSYNC SPI TIMING REQUIREMENTS t Setup time between the data and ...
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CLK+ CLK– CH A/CH B DATA A N – A/CH B FAST A DETECT N – 7 DCO+ DCO– Figure 3. LVDS Mode Data and Fast Detect Output Timing (Fast Detect Mode 1 Through Fast Detect Mode 5) ...
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AD9640 ABSOLUTE MAXIMUM RATINGS Table 9. Parameter ELECTRICAL AVDD, DVDD to AGND DRVDD to DRGND AGND to DRGND AVDD to DRVDD VIN+A/VIN+B, VIN−A/VIN−B to AGND CLK+, CLK− to AGND SYNC to AGND VREF to AGND SENSE to AGND CML to ...
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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS DRVDD D10B D11B D12B D13B (MSB) DCOB DCOA D0A (LSB) NOTES CONNECT. 2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS ...
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AD9640 Pin No. Mnemonic Type ADC Fast Detect Outputs 29 FD0A Output 30 FD1A Output 31 FD2A Output 32 FD3A Output 53 FD0B Output 54 FD1B Output 55 FD2B Output 56 FD3B Output Digital Inputs 52 SYNC Input Digital Outputs ...
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DRVDD D1– D1+ D2– D2+ D3– D3+ D4– D4+ DCO– DCO+ D5– D5+ D6– D6+ D7– NOTES CONNECT. 2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. ...
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AD9640 Pin No. Mnemonic Type Digital Inputs 52 SYNC Input Digital Outputs 63 D0+ (LSB) Output 62 D0− (LSB) Output 3 D1+ Output 2 D1− Output 5 D2+ Output 4 D2− Output 7 D3+ Output 6 D3− Output 9 D4+ ...
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EQUIVALENT CIRCUITS VIN Figure 8. Equivalent Analog Input Circuit AVDD 1.2V 10kΩ 10kΩ CLK+ Figure 9. Equivalent Clock Input Circuit DRVDD DRGND Figure 10. Digital Output DRVDD DVDD 26kΩ 1kΩ SDIO/DCS Figure 11. Equivalent SDIO/DCS or SMI SDFS Circuit CLK– ...
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AD9640 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V; DVDD = 1.8 V; DRVDD = 3.3 V; sample rate = 150 MSPS, DCS enabled internal reference p-p differential input; VIN = −1.0 dBFS; and 64k sample; T ...
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SNR = 65dBc (66dBFS) –20 ENOB = 10.4 BITS SFDR = 70.0dB –40 SECOND HARMONIC –60 THIRD HARMONIC –80 –100 –120 FREQUENCY (MHz) Figure 22. AD9640-150 Single-Tone FFT with ...
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AD9640 120 SFDR (dBFS) 100 80 SNR (dBFS SFDR (dBc) 20 85dB REFERENCE LINE 0 –90 –80 –70 –60 –50 –40 INPUT AMPLITUDE (dBFS) Figure 28. AD9640-150 Single-Tone SNR/SFDR vs. Input Amplitude (A with f = 2.3 MHz ...
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SFDR (dBc) –40 –60 IMD3 (dBc) IMD3 (dBFS) –80 SFDR (dBFS) –100 –120 –90 –78 –66 –54 –42 INPUT AMPLITUDE (dBFS) Figure 34. AD9640-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (A with f = 169.1 MHz 172.1 ...
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AD9640 – – – – OUTPUT CODE Figure 40. AD9640 Grounded Input Histogram ...
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THEORY OF OPERATION The AD9640 dual ADC design can be used for diversity reception of signals, where the ADCs are operating identically on the same carrier but from two separate antennae. The ADCs can also be operated with independent analog ...
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AD9640 The output common-mode voltage of the with the CML pin of the AD9640 (see Figure 46), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. 499Ω p-p ...
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VOLTAGE REFERENCE A stable and accurate voltage reference is built into the AD9640. The input range can be adjusted by varying the reference voltage applied to the AD9640, using either the internal reference or an externally applied reference voltage. The ...
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AD9640 2.5 2.0 1.5 1.0 0 –0.5 –1.0 –1.5 –2.0 –2.5 –40 – TEMPERATURE (°C) Figure 54. Typical VREF Drift When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an ...
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CLK+ can be directly driven from a CMOS gate. Although the CLK+ input circuit supply is AVDD (1.8 V), this input is designed to withstand input voltages up to 3.6 V, making the selection of the drive logic voltage very ...
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AD9640 POWER DISSIPATION AND STANDBY MODE As shown in Figure 63, the power dissipated by the AD9640 is proportional to its sample rate. In CMOS output mode, the digital power dissipation is determined primarily by the strength of the digital ...
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DIGITAL OUTPUTS The AD9640 output drivers can be configured to interface with 1 3.3 V CMOS logic families by matching DRVDD to the digital supply of the interfaced logic. The AD9640 can also be configured for LVDS outputs ...
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AD9640 ADC OVERRANGE AND GAIN CONTROL In receiver applications desirable to have a mechanism to reliably determine when the converter is about to be clipped. The standard overflow indicator provides after-the-fact infor- mation on the state of the ...
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When the fast detect mode select bits are set to 0b001, 0b010, or 0b011, a subset of the fast detect output pins is available. In these modes, the fast detect output pins have a latency of six clock cycles. Table ...
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AD9640 similarly, corresponds to the fine lower threshold bits, except that it is asserted only if the input magnitude is less than the value programmed in the fine lower threshold register after the dwell time elapses. The dwell time is ...
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SIGNAL MONITOR The signal monitor block provides additional information about the signal being digitized by the ADC. The signal monitor computes the rms input magnitude, the peak magnitude, and/or the number of samples by which the magnitude exceeds a particular ...
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AD9640 Figure 69 illustrates the rms magnitude monitoring logic. FROM MEMORY MAP SIGNAL MONITOR DOWN PERIOD REGISTER COUNTER LOAD FROM CLEAR LOAD INPUT SIGNAL MONITOR PORTS ACCUMULATOR REGISTER (SMR) Figure 69. ADC Input RMS Magnitude Monitoring Block Diagram For rms ...
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DC Correction Bandwidth The dc correction circuit is a high-pass filter with a programmable bandwidth (ranging between 0.15 Hz and 1.2 kHz at 125 MSPS). The bandwidth is controlled by writing Bits[5:2] of the signal monitor dc correction control register, ...
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AD9640 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST The AD9640 includes built-in test features to enable verification of the integrity of each channel as well as to facilitate board level debugging. A built-in self-test (BIST) feature is included that verifies the ...
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CHANNEL/CHIP SYNCHRONIZATION The AD9640 has a SYNC input that allows the user flexible synchronization options for synchronizing the internal blocks. The clock divider sync feature is useful to guarantee synchronized sample clocks across multiple ADCs. The signal monitor block can ...
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AD9640 SERIAL PORT INTERFACE (SPI) The AD9640 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. This gives the user added flexibility and customization ...
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CONFIGURATION WITHOUT THE SPI In applications that do not interface to the SPI control registers, the SDIO/DCS pin, the SCLK/DFS pin, the SMI SDO/OEB pin, and the SMI SCLK/PDWN pin serve as standalone, CMOS- compatible control pins. When the device ...
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AD9640 MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map table has eight bit locations. The memory map is roughly divided into four sections: chip configura- tion and ID register map (Address 0x00 to Address 0x02); ...
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EXTERNAL MEMORY MAP Table 25. Memory Map Registers Addr Register Bit 7 (Hex) Name (MSB) Bit 6 Chip Configuration Registers 0x00 SPI Port 0 LSB first Configuration (Global) 0x01 Chip ID (Global) 0x02 Chip Grade Open Open (Global) Channel Index ...
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AD9640 Addr Register Bit 7 Bit 6 (Hex) Name (MSB) 0x0E BIST Enable Open Open (Local) 0x10 Offset Adjust Open Open (Local) 0x14 Output Mode Drive Output type strength 0 = CMOS 3 LVDS ...
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Addr Register Bit 7 Bit 6 (Hex) Name (MSB) 0x10C Signal Monitor Open DC DC Correction correction Control freeze (Global) 0x10D Signal Monitor DC Value Channel A Register 0 (Global) 0x10E Signal Monitor Open Open DC Value Channel A Register ...
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AD9640 Addr Register Bit 7 Bit 6 (Hex) Name (MSB) 0x11A Signal Monitor Result Channel B Register 1 (Global) 0x11B Signal Monitor Open Open Result Channel B Register 2 (Global) MEMORY MAP REGISTER DESCRIPTION For additional information about functions controlled ...
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Table 26. DC Correction Bandwidth DC Correction Control Register 0x10C[5:2] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Bit 1—DC Correction for Signal Path Enable Setting Bit 1 high causes the output ...
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AD9640 Signal Monitor Result Channel A (Register 0x116 to Register 0x118) Register 0x116, Bits[7:0]—Signal Monitor Result Channel A[7:0] Register 0x117, Bits[7:0]—Signal Monitor Result Channel A[15:8] Register 0x118, Bits[7:4]—Reserved Register 0x118, Bits[3:0]—Signal Monitor Result Channel A[19:16] This 20-bit value contains the ...
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APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting design and layout of the AD9640 as a system recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. Power ...
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AD9640 OUTLINE DIMENSIONS PIN 1 INDICATOR TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING PLANE PIN 1 INDICATOR TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING PLANE 9.00 BSC SQ 0.60 MAX 49 48 0.50 8.75 BSC BSC SQ 0.50 ...
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... AD9640ABCPZ-105 1, 2 −40°C to +85° AD9640ABCPZ-80 −40°C to +85°C AD9640ABCPZRL7- −40°C to +85°C 1 AD9640BCPZ-150 −40°C to +85°C 1 AD9640BCPZ-125 −40°C to +85°C 1 AD9640BCPZ-105 −40°C to +85°C 1 AD9640BCPZ-80 −40°C to +85°C 1 AD9640-150EBZ 1 AD9640-125EBZ 1 AD9640-105EBZ ...
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AD9640 NOTES ©2007–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06547-0-12/09(B) Rev Page ...