ADC0804LCN Intersil, ADC0804LCN Datasheet - Page 11

• Manufacturer Part Number: ADC0804LCN
• Description: IC ADC 8-BIT 10KSPS 1LSB 20-DIP
• Manufacturer: Intersil

Specifications of ADC0804LCN

• Number Of Bits: 8
• Sampling Rate (per Second): 10k
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 20-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ADC0804LCNIN; ADC0804LCNIN

function. IC voltage regulators may be used for references if
the ambient temperature changes are not excessive.
Zero Error
The zero of the A/D does not require adjustment. If the
minimum analog input voltage value, V
zero offset can be done. The converter can be made to output
0000 0000 digital code for this minimum input voltage by
biasing the A/D V
Applications section). This utilizes the differential mode
operation of the A/D.
The zero error of the A/D converter relates to the location of
the first riser of the transfer function and can be measured by
grounding the V
positive voltage to the V
between the actual DC input voltage which is necessary to
just cause an output digital code transition from 0000 0000 to
0000 0001 and the ideal
V
Full Scale Adjust
The full scale adjustment can be made by applying a
differential input voltage which is 1
desired analog full scale voltage range and then adjusting
the magnitude of the V
code which is just changing from 1111 1110 to 1111 1111.
When offsetting the zero and using a span-adjusted V
voltage, the full scale adjustment is made by inputting V
to the V
V
where:
V
V
(Both are ground referenced.)
Clocking Option
The clock for the A/D can be derived from an external source
such as the CPU clock or an external RC network can be
added to provIde self-clocking. The CLK IN (pin 4) makes
use of a Schmitt trigger as shown in Figure 16.
Heavy capacitive or DC loading of the CLK R pin should be
avoided as this will disturb normal converter operation.
V
REF
IN(+)
MAX
MIN
IN +
/2 = 2.500V).
= the low end (the offset zero) of the analog range.
CLK IN
f
= the high end of the analog input range, and
input which is given by:
SADJ
IN(-)
R
C
FIGURE 16. SELF-CLOCKING THE A/D
input of the A/D and applying a voltage to the
=
CLK R
V
IN(-)
MAX
IN(-)
input and applying a small magnitude
–
input at this V
1.5
REF
IN(+)
1
/
2
-----------------------------------------
19
/2 input (pin 9) for a digital output
V
4
LSB value (
input. Zero error is the difference
MAX
11
ADC0803-
ADC0804
256
–
lN(MlN)
1
V
/
2
MIN
lN(MlN)
LSB down from the
CLK
1
/
2
value (see
,
LSB = 9.8mV for
f
R
, is not ground, a
CLK
10k
1.1 RC
ADC0803, ADC0804
1
REF
MlN
/2
Loads less than 50pF, such as driving up to 7 A/D converter
clock inputs from a single CLK R pin of 1 converter, are
allowed. For larger clock line loading, a CMOS or low power
TTL buffer or PNP input logic should be used to minimize the
loading on the CLK R pin (do not use a standard TTL buffer).
Restart During a Conversion
If the A/D is restarted (CS and WR go low and return high)
during a conversion, the converter is reset and a new
conversion is started. The output data latch is not updated if
the conversion in progress is not completed. The data from
the previous conversion remain in this latch.
Continuous Conversions
In this application, the CS input is grounded and the WR
input is tied to the INTR output. This WR and INTR node
should be momentarily forced to logic low following a power-
up cycle to insure circuit operation. See Figure 17 for details.
Driving the Data Bus
This CMOS A/D, like MOS microprocessors and memories,
will require a bus driver when the total capacitance of the
data bus gets large. Other circuItry, which is tied to the data
bus, will add to the total capacitive loading, even in three-
state (high-impedance mode). Back plane busing also
greatly adds to the stray capacitance of the data bus.
There are some alternatives available to the designer to
handle this problem. Basically, the capacitive loading of the
data bus slows down the response time, even though DC
specifications are still met. For systems operating with a
relatively slow CPU clock frequency, more time is available
in which to establish proper logic levels on the bus and
therefore higher capacitive loads can be driven (see Typical
Performance Curves).
At higher CPU clock frequencies time can be extended for
I/O reads (and/or writes) by inserting wait states (8080) or
using clock-extending circuits (6800).
START
150pF
N.O.
ANALOG
FIGURE 17. FREE-RUNNING CONNECTION
INPUTS
10
ADC0803 - ADC0804
1
2
3
4
5
6
7
8
9
10K
CS
RD
WR
CLK IN
INTR
V
V
AGND
V
DGND
IN
IN
REF
(+)
(-)
/2
CLK R
DB
DB
DB
DB
DB
DB
DB
DB
V+
6
7
0
1
2
3
4
5
20
19
18
17
16
15
14
13
12
11
LSB
MSB
5V (V
DATA
OUTPUTS
REF
+
10 F
)