MAX11800EWC+T Maxim Integrated Products, MAX11800EWC+T Datasheet - Page 33

• Manufacturer Part Number: MAX11800EWC+T
• Description: IC TOUCH SCREEN CTLR 12-WLP
• Manufacturer: Maxim Integrated Products
• Type: Resistiver

Specifications of MAX11800EWC+T

• Touch Panel Interface: 4-Wire
• Number Of Inputs/keys: 1 TSC
• Resolution (bits): 12 b
• Data Interface: Serial, SPI™
• Data Rate/sampling Rate (sps, Bps): 105k
• Voltage - Supply: 1.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 12-WLP
• Voltage Supply Source: Single Supply
• Sampling Rate (per Second): 105k
• Resolution: 11 bits
• Interface Type: I2C, SPI
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.7 V
• Conversion Rate: 34.4 KSPs
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MAX11800EWC+T; MAX11800EWC+TTR

The MAX11800/MAX11801 support a low-power power-
down mode suspending all touch-screen activity and
the panel is not driven. In this mode, the
MAX11800/MAX11801 is unable to detect a touch.
When commanded to transition from PWRDN to any
normal mode of operation, the MAX11800/MAX11801
go through a PUR/PUF sequence prior to observing the
panel touch status, minimizing the occurrence of inter-
rupts issued by false touches caused by the initial state
of panel capacitances.
In addition, when commanded to transition between
normal operating modes, the MAX11800/MAX11801
clear any existing interrupts and go through the
PUR/PUF sequence prior to observing the current panel
touch status.
The MAX11800/MAX11801 include an internal FIFO to
store scan block results for readback through the AP.
Each scan block result contains complete data for all
measurements requested by the scan type (X, Y; or X,
Y, Z1; or X, Y, Z1, Z2). The depth of each scan data
block ranges from 32 bits (X, Y mode) to 48 bits (X, Y,
Z1 mode) or 64 bits (X, Y, Z1, and Z2 mode).
The internal FIFO stores up to 16 complete scan
blocks, a total of 1024 bits. Regularly service the FIFO
to prevent overflow conditions. In the event of an over-
flow, the FIFO ceases to write new data until the old
data is read or cleared. Avoid overflow to prevent data
loss and unreliable behavior.
Check the general status register (0x00) and the FIFO
overflow bit to determine if the FIFO is in overflow. The
FIFO overflow bit asserts when a data overflow occurs.
See the Clearing FIFO section.
Write to the operating mode configuration register
(0x0B) to clear the FIFO. Modifying the contents of the
register is not necessary as any write operation to this
register location clears the FIFO and the interrupt TIRQ
(if present).
Low-Power, Ultra-Small Resistive Touch-Screen
Delayed Touch Detection During Mode Transitions
______________________________________________________________________________________
Controllers with I
Clearing FIFO
FIFO Memory
The FIFO completely clears when autonomous conver-
sions halt and the MAX11800/MAX11801 transition to
direct conversion mode. The FIFO also clears on transi-
tions from direct conversion mode to autonomous
mode.
Table 10 illustrates the scan data block structure within
the FIFO for each scan type. Block boundaries are indi-
cated by bold lines. Numeric subscripts denote the
sample order when the data was taken. Readback pro-
ceeds from top to bottom. FIFO blocks are written as a
complete unit with an interrupt issued only after all
required block measurements are complete and data is
tagged. A FIFO data block consists of 2, 3, or 4 FIFO
data words (word = 16 bits).
Table 10. FIFO Data Block Structure
X
X
Y
Y
X
X
Y
Y
X
X
Y
Y
X
X
Y
Y
2-WORD BLOCK
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
MSB
MSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
LSB
MSB
LSB
LSB
(X, Y)
2
FIFO Data Block Readback Structure
C/SPI Interface
X
X
Y
Y
Z1
Z1
X
X
Y
Y
Z2
Z2
3-WORD BLOCK
1
1
1
1
2
2
2
2
1
1
2
2
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
(X, Y, Z1)
.
.
.
.
X
X
Y
Y
Z1
Z1
Z2
Z2
X
X
Y
Y
Z1
Z1
Z2
Z2
4-WORD BLOCK
1
1
1
1
2
2
2
2
1
1
1
1
2
2
2
2
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
(X, Y, Z1, Z2)
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
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