MAX11800ETC+ Maxim Integrated Products, MAX11800ETC+ Datasheet - Page 42

IC CTRLR TOUCH-SCREEN 12-TQFN

MAX11800ETC+

Manufacturer Part Number
MAX11800ETC+
Description
IC CTRLR TOUCH-SCREEN 12-TQFN
Manufacturer
Maxim Integrated Products
Type
Resistiver
Datasheet

Specifications of MAX11800ETC+

Touch Panel Interface
4-Wire
Number Of Inputs/keys
1 TSC
Resolution (bits)
12 b
Data Interface
Serial, SPI™
Data Rate/sampling Rate (sps, Bps)
105k
Voltage - Supply
1.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
12-TQFN Exposed Pad
Voltage Supply Source
Single Supply
Sampling Rate (per Second)
105k
Resolution
11 bits
Interface Type
I2C, SPI
Supply Voltage (max)
3.6 V
Supply Voltage (min)
1.7 V
Conversion Rate
34.4 KSPs
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Low-Power, Ultra-Small Resistive Touch-Screen
Controllers with I
master-generated 9th clock pulse if the previous byte is
successfully received. Monitoring ACK allows for detec-
tion of unsuccessful data transfers. An unsuccessful
data transfer occurs if a receiving device is busy or if a
system fault has occurred. In the event of an unsuc-
cessful data transfer, the bus master retries communica-
tion. The master pulls down SDA during the 9th clock
cycle to acknowledge receipt of data when the
MAX11801/MAX11803 are in read mode. An acknowl-
edge is sent by the master after each read byte to allow
data transfer to continue. A not-acknowledge is sent
when the master reads the final byte of data from the
MAX11801/MAX11803, followed by a STOP condition.
A minimum write sequence to the MAX11801/
MAX11803 includes transmission of a START condition,
the slave address with the R/W bit set to 0, 1 byte of
data to select the internal register address pointer, 1
byte of data written to the selected register, and a
STOP condition. Figure 25 illustrates the proper frame
format for writing 1 byte of data to the MAX11801/
MAX11803. Figure 26 illustrates the frame format for
writing N-bytes of data to the MAX11801/MAX11803.
The slave address with the R/W bit set to 0 indicates
that the master intends to write data to the
MAX11801/MAX11803. The MAX11801/MAX11803
acknowledge receipt of the address byte during the
master-generated 9th SCL pulse.
Figure 25. I
Figure 26. I
42
SDA
SCL
SDA
SCL
START
______________________________________________________________________________________
START
2
2
C Single Write Sequence
C Multiple Write Sequence
1
BYTE 1: DEVICE ADDRESS
0
WRITE ADDRESS
0
ACKNOWLEDGE GENERATED BY MAX11801/MAX11803
1
1
0
BYTE 1: DEVICE ADDRESS
0
A1 A0
WRITE ADDRESS
0
W
1
A
N6
0
Write Data Format
ACKNOWLEDGE GENERATED BY MAX11801/MAX11803
WRITE REGISTER NUMBER
BYTE 2: REG NUMBER = N
N5
A1 A0
N4
N3 N2 N1 N0 X
W
2
A
C/SPI Interface
N6
BYTE 2: FIRST REG NUMBER = N
A
N5
WRITE REGISTER NUMBER
D
BYTE 3: REG(N)[7:0] DATA
D
N4
D
WRITE DATA
N3 N2 N1 N0
D
D
The second byte transmitted from the master config-
ures the MAX11801/MAX11803’s internal register
address pointer. The pointer tells the MAX11801/
MAX11803 where to write the next byte of data. Note
that the MAX11801/MAX11803 use a 7-bit register
pointer format, and the selection should be left-justified
within the register byte (the last bit in the register byte is
a don’t care). An acknowledge pulse is sent by the
MAX11801/MAX11803 upon receipt of the address
pointer data.
The third byte sent to the MAX11801/MAX11803 contains
the data that is written to the chosen register. An
acknowledge pulse from the MAX11801/MAX11803 sig-
nals receipt of the data byte. The MAX11801/
MAX11803 do not support autoincrement in write
mode. However, by repeating multiple register address
byte + data byte pairs (bytes 2 and 3 in Figure 25) the
user can perform multiple register writes within a single
transfer. There is no limit as to how many registers
the user can write with a single command sequence,
but only commands listed as “pairable” can be
sequenced in this manner. For example, the I
can perform multiple register writes to set up all required
conversion options and then issue a separate I
mand to start a conversion process. Figure 26 illustrates
how to write to multiple registers with one frame. The
master signals the end of transmission by issuing a
STOP condition. Register addresses greater than 0x0B
are reserved. Do not write to these addresses.
ACKNOWLEDGE GENERATED BY I
D
D
ACKNOWLEDGE GENERATED BY I
D
A
X
Z
WRITE REGISTER NUMBER
BYTE 4: REG NUMBER = Z
Z
A
Z
D
Z
D
Z
BYTE 3: REG(N)[7:0] DATA
2
C MASTER
Z
2
C MASTER
D
WRITE DATA
Z
X
D
A
D
D
D
BYTE 5: REG(Z)[7:0] DATA
D
D
WRITE DATA
D
D
D
D
D
A
D
D
2
C master
2
A
STOP
C com-
STOP

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