MAX11800ETC/V+ Maxim Integrated Products, MAX11800ETC/V+ Datasheet - Page 41

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MAX11800ETC/V+

Manufacturer Part Number
MAX11800ETC/V+
Description
IC TOUCH SCREEN CTRLR LP 12WQFN
Manufacturer
Maxim Integrated Products
Type
Resistiver
Datasheet

Specifications of MAX11800ETC/V+

Touch Panel Interface
4-Wire
Number Of Inputs/keys
1 TSC
Resolution (bits)
12 b
Data Interface
Serial, SPI™
Data Rate/sampling Rate (sps, Bps)
105k
Voltage - Supply
1.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
12-WQFN Exposed Pad
Voltage Supply Source
Single Supply
Sampling Rate (per Second)
105k
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 22. 2-Wire Interface Timing Diagram
on SDA with SCL high. A STOP condition is a low-to-
high transition on SDA while SCL is high (Figure 23). A
START condition from the master signals the beginning
of a transmission to the MAX11801/MAX11803. The
master terminates transmission and frees the bus by
issuing a STOP condition. The bus remains active if a
repeated START condition is generated instead of a
STOP condition.
The MAX11801/MAX11803 recognize a STOP condition
at any point during data transmission, except if the
STOP condition occurs in the same high pulse as a
START condition. For proper operation, do not send a
STOP condition during the same SCL high pulse as the
START condition.
The slave address is defined as the seven most signifi-
cant bits (MSBs) followed by the read/write bit (R/W). For
the MAX11801/MAX11803 the seven most significant bits
Figure 23. START, STOP, and Repeated START Conditions
Low-Power, Ultra-Small Resistive Touch-Screen
SCL
SDA
SDA
SCL
S
S
t
______________________________________________________________________________________
F
t
HD;STA
t
LOW
t
R
Early STOP Conditions
Sr
t
HD;DAT
Controllers with I
Slave Address
t
HIGH
t
SU;DAT
t
F
P
t
SU;STA
Sr
are 10010 A1 A0, where A1 and A0 are user config-
urable through the address input pins A1 and A0. The
LSB is the read/write bit. Setting the R/W bit to 1 config-
ures the MAX11801/MAX11803 for read mode. Setting
the R/W bit to 0 configures the MAX11801/MAX11803
for write mode. The address is the first byte of informa-
tion sent to the MAX11801/MAX11803 after the START
condition. See Figures 25 and 26 for details.
The register addresses are defined as the seven most
significant bits (MSBs) followed by a don’t care bit. The
format is N N N N N N N X, where N is the register
address and X is a don’t care.
The acknowledge bit (ACK) is a clocked 9th bit that the
MAX11801/MAX11803 use to handshake receipt each
byte of data when in write mode (see Figure 24). The
MAX11801/MAX11803 pull down SDA during the entire
Figure 24. Acknowledge
t
HD;STA
CONDITION
SDA
SCL
START
I
2
t
SP
C Slave Address = 1 0 0 1 0 A1 A0 R/W
1
2
C/SPI Interface
28
t
SU;STO
NOT ACKNOWLEDGE
I
2
P
C Register Address
ACKNOWLEDGE
ACKNOWLEDGEMENT
t
BUF
CLOCK PULSE FOR
Acknowledge
S
9
41

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