TDA8754HL/11/C1,55 NXP Semiconductors, TDA8754HL/11/C1,55 Datasheet

IC TRPL 8BIT VIDEO ADC 144LQFP

TDA8754HL/11/C1,55

Manufacturer Part Number
TDA8754HL/11/C1,55
Description
IC TRPL 8BIT VIDEO ADC 144LQFP
Manufacturer
NXP Semiconductors
Type
Video ADCr
Datasheet

Specifications of TDA8754HL/11/C1,55

Package / Case
144-LQFP
Resolution (bits)
8 b
Sampling Rate (per Second)
110M
Data Interface
Serial
Voltage Supply Source
Analog and Digital
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-10°C ~ 70°C
Mounting Type
Surface Mount
Operating Supply Voltage
3 V to 3.6 V
Supply Current
180 mA
Maximum Operating Temperature
+ 70 C
Maximum Power Dissipation
1.3 W
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-3594
935272702551
TDA8754HL11BE-S

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TDA8754HL/11/C1,55
Manufacturer:
NXP Semiconductors
Quantity:
10 000
1. General description
2. Features
The TDA8754 is a complete triple 8-bit ADC with an integrated PLL running up to
270 Msample/s and analog preprocessing functions (clamp and PGA) optimized for
capturing RGB/YUV graphic signals.
The PLL generates a pixel clock from inputs HSYNC and COAST.
The TDA8754 offers full sync processing for sync-on-green applications. A clamp signal
may be generated internally or provided externally.
The clamp levels, gains and other settings are controlled via the I
This IC supports display resolutions up to QXGA (2048
TDA8754
Triple 8-bit video ADC up to 270 Msample/s
Rev. 06 — 16 June 2005
3.3 V power supply
Temperature range from 10 C to +70 C
Triple 8-bit ADC:
Analog sampling rate from 12 Msample/s up to 270 Msample/s
Maximum data rate:
PLL control via I
Three clamp circuits for programming a clamp code from 24 to +136 by steps of
1 LSB (mid-scale clamping for YUV signal)
Internal generation of clamp signal
Three independent blanking functions
Input:
0.25 LSB Differential Non-Linearity (DNL)
0.6 LSB Integral Non-Linearity (INL)
Single port mode: 140 MHz
Dual port mode: 270 MHz
3.3 V LV-TTL outputs
390 ps PLL jitter peak to peak at 270 MHz
Low PLL drift with temperature (2 phase steps maximum)
PLL generates the ADC sampling clock which can be locked on the line frequency
from 15 kHz to 150 kHz
Integrated PLL divider
Programmable phase clock adjustment cells
700 MHz analog bandwidth
Two independent analog inputs selectable via I
2
C-bus:
2
C-bus
1536) at 85 Hz.
Product data sheet
2
C-bus interface.

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TDA8754HL/11/C1,55 Summary of contents

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TDA8754 Triple 8-bit video ADC up to 270 Msample/s Rev. 06 — 16 June 2005 1. General description The TDA8754 is a complete triple 8-bit ADC with an integrated PLL running up to 270 Msample/s and analog preprocessing functions (clamp ...

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Philips Semiconductors Analog input from 0 (p-p) to produce a full-scale ADC input (p-p) Three controllable amplifiers: gain control via I peak-to-peak output with a half LSB resolution Synchronization: Frame and field detection ...

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Philips Semiconductors 5. Ordering information Table 2: Ordering information Type number Package Name TDA8754HL/11 LQFP144 TDA8754HL/14 TDA8754HL/17 TDA8754HL/21 TDA8754HL/27 [1] TDA8754EL/11 LBGA208 TDA8754EL/14 TDA8754EL/17 TDA8754EL/21 TDA8754EL/27 [1] Values are not yet guaranteed. 6. Block diagram RGB1 input RGB2 input TDA8754 ...

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Philips Semiconductors 7. Pinning information 7.1 Pinning Fig 2. Pin configuration LQFP144 package Fig 3. Pin configuration LBGA208 package 7.2 Pin description Table 3: Symbol GNDD(TTL) V CCD(TTL) HSYNC2 CHSYNC2 V CCA(PLL) HSYNC1 CHSYNC1 9397 750 14984 Product data sheet ...

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Philips Semiconductors Table 3: Symbol GNDA(PLL) CZ GNDA(CPO) CP PMO GNDA(SUB) CAPSOGIN1 CAPSOGO CAPSOGIN2 GNDA(SOG) SOGIN1 V CCA(SOG) SOGIN2 V CCA(R) RIN1 GNDA(R1) RIN2 GNDA(R2) DEC RBOT RCLPC V CCA(G) GIN1 GNDA(G1) GIN2 GNDA(G2) GBOT GCLPC V CCA(B) BIN1 GNDA(B1) ...

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Philips Semiconductors Table 3: Symbol BB0 BB1 BB2 BB3 BB4 BB5 BB6 BB7 V CCO(BB) GNDO(BB) BOR BA0 BA1 BA2 BA3 BA4 BA5 BA6 BA7 V CCO(BA) GNDO(BA) GB0 GB1 GB2 GB3 GB4 GB5 GB6 GB7 V CCO(GB) GNDO(GB) GOR ...

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Philips Semiconductors Table 3: Symbol GNDO(GA) RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 V CCO(RB) GNDO(RB) ROR RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 V CCO(RA) GNDO(RA) V CCO(CLK) CKDATA GNDO(CLK) GNDD(I2C) V CCD(I2C) A0 SDA SCL DIS ...

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Philips Semiconductors Table 3: Symbol V CCO(TTL) VSYNCO FIELDO CLPO CKREFO CSYNCO ACRX2 ACRX1 GNDD(SLC) V CCD(SLC) CKEXT COAST VSYNC2 VSYNC1 Table 4: Symbol SOGIN1 GNDA(PLL) SOGIN2 GNDA(PLL) HSYNC2 CHSYNC2 COAST CSYNCO FIELDO HSYNCO SCL n.c. n.c. DIS A0 CKDATA ...

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Philips Semiconductors Table 4: Symbol VSYNCO DEO SDA n.c. n.c. n.c. GNDO(CLK) V CCO(CLK) RIN1 GNDA CAPSOGIN1 CAPSOGIN2 CAPSOGO HSYNC1 VSYNC1 CLPO n.c. n.c. TCK TDO V CCD(I2C) n.c. n.c. n.c. GNDA GNDA CZ CP GNDA(CPO) CHSYNC1 VSYNC2 HPDO n.c. ...

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Philips Semiconductors Table 4: Symbol GNDA GNDA GNDA GNDD(TTL) V CCD(TTL) GNDD(SLC) V CCD(SLC) n.c. n.c. n.c. n.c. GNDA GNDA RBOT GNDA n.c. n.c. n.c. n.c. GIN1 GNDA DEC V CCA V CCA n.c. n.c. n.c. n.c. n.c. GNDA GNDA ...

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Philips Semiconductors Table 4: Symbol GBOT GNDA GCLPC n.c. n.c. n.c. n.c. n.c. GNDA GNDA GNDA BCLPC V CCA n.c. n.c. n.c. n.c. n.c. BIN1 GNDA BBOT V CCA n.c. n.c. n.c. n.c. GNDA GNDA AGCO TEST V CCO V ...

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Philips Semiconductors Table 4: Symbol GNDD(ADC) BA2 V CCO GB4 GB0 GA4 GA0 GNDO PWD n.c. n.c. n.c. n.c. V CCD(ADC) V CCD(ADC) BB1 BA6 BA3 BOR GB5 GB1 GA5 GA1 RB6 RB3 RB0 RA5 RA2 ROR BB6 BB4 BB2 ...

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Philips Semiconductors Table 4: Symbol RB1 RA6 RA3 RA0 BB7 BB5 BB3 BB0 BA5 BA1 GB7 GB3 GA7 GA3 GOR RB5 RB2 RA7 RA4 RA1 8. Functional description 8.1 Functional description This triple high-speed 8-bit ADC is designed to convert ...

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Philips Semiconductors 8.1.1.2 Power-down mode In Power-down mode the status of the blocks is as follows: • All digital inputs and outputs are in high-impedance state • All blocks are inactive (I • Analog output is left uncontrolled • 2 ...

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Philips Semiconductors The reference ladders regulators are integrated. 8.2.4 Clamp Three independent parallel clamping circuits are used to clamp the video input signals on programmable black levels. The clamp levels may be set from 24 to +136 LSBs in steps ...

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Philips Semiconductors Bit SCHCKREFO is used if in demultiplexed mode one pixel shift is needed in the DEO signal (to move the screen one vertical line). By setting bit SCHCKREFO from a logic logic 1 a left ...

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Philips Semiconductors The maximum hum perturbation is 250 mV (p- have a correct SOG functionality. Table 5: BITS SOGI[1: [1] Definitions: — Tvideo = total time in 2 frames when video signal ...

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Philips Semiconductors 8.9 3-level When the synchronization pulse of the input of the SOG is 3-level, the system will be able to detect that a 3-level sync is present and will advise the customer if a change is observed by ...

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Philips Semiconductors Table 8: Bit Byte Byte Byte 9.1.2 Write all registers All registers are programmed one after the other, by giving this ...

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Philips Semiconductors Table 11: Bit Byte Byte Byte ( 9.1.2.1 Read register Table 12: SDA line Description S Byte 1 A Byte ...

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Philips Semiconductors Table 13: Bits Byte 4 Byte 5 Table 14: Bit Byte Byte Byte Byte Byte 5 ...

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I C-bus registers overview 2 Table 15: I C-bus analog write registers Addr Name Bit MSB 7 6 00h OFFSETR OR7 OR6 01h COARSER OR8 CR6 02h FINER - - 03h OFFSETG OG7 OG6 04h COARSEG OG8 CG6 ...

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Table 15: I C-bus analog write registers …continued Addr Name Bit MSB 7 6 19h OUTPUTEN2 CKROEN CSOEN 1Ah CLKOUTPUT - - 1Bh INTOSC - - 1Ch reserved 1Dh reserved 1Eh PWRMGT - - 1Fh READADDR - - 2 ...

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Philips Semiconductors 9.3 Offset registers (R, G and B) The offset registers contain a 9-bit value which controls the clamp level for the RGB channels. The 8 LSBs are in the offset registers and the 1 MSB is in the ...

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Philips Semiconductors Table 19: Value : 086h 087h 9.4 Coarse registers (R, G and B) The coarse gain of the AGC is controlled with 7 bits. The code gain can vary from 32 to 95; see Table 20: Register COARSER ...

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Philips Semiconductors Table 22: Value 9.5 Fine registers (R, G and B) Fine gain control is done with 3 bits allowing 8 intermediate values between two values of consecutive coarse gain. Table 23: Register FINER (02h) FINEG ...

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Philips Semiconductors 9.6 Sync-on-green register Table 26: SOG - sync-on-green register (address 09h) bit allocation Bit 7 6 Symbol DO UP Reset 0 0 Access W W Table 27: SOG - sync-on-green register (address 09h) bit description Bit Symbol Description ...

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Philips Semiconductors Table 29: PLLCTRL - PLL control register (address 0Ah) bit description Bit Symbol Description IP[1:0] charge pump current value to increase the bandwidth of the PLL 00 = 800 1200 A 10 ...

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Philips Semiconductors Table 32: Phase registers bits PA4 PA3 Table 33: VCO gain control VCO2 VCO1 ...

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Philips Semiconductors Table 36: DIVLSB - PLL divider ratio (LSB) register (address 0Dh) bit allocation Bit 7 Symbol DI7 DI6 Reset 1 Access W Table 37: DIVLSB - PLL divider ratio (LSB) register (address 0Dh) bit description Bit Symbol Description ...

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Philips Semiconductors 9.11 Coast register Remark: When POSTCOAST[4:0] = PRECOAST[2: then the coast pulse equals the VSYNC input. Table 41: COAST - coast register (address 12h) bit allocation Bit 7 Symbol PRE PRE COAST2 COAST1 Reset 0 Access ...

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Philips Semiconductors 9.13 Vertical sync selection register Table 45: VSYNCSEL - vertical sync selection register (address 14h) bit allocation Bit 7 Symbol - Reset X Access W Table 46: VSYNCSEL - vertical sync selection register (address 14h) bit description Bit ...

Page 33

Philips Semiconductors Table 48: CLAMP - clamp register (address 15h) bit description Bit Symbol 4 CLPSEL1 3 CLPH 2 CLPENL 1 ICLP 0 CLPT 9.15 Inverter register Table 49: INVERTER - inverter register (address 16h) bit allocation Bit 7 6 ...

Page 34

Philips Semiconductors Table 50: INVERTER - inverter register (address 16h) bit description Bit Symbol 1 VSOINVRGB 0 FIELDOINV 9.16 Output register Table 51: OUTPUT - output register (address 17h) bit allocation Bit 7 Symbol RGBSEL TEN Reset 0 Access W ...

Page 35

Philips Semiconductors 9.17 Output enable register 1 Table 53: OUTPUTEN1 - output enable 1 register (address 18h) bit allocation Bit 7 Symbol - Reset X Access W W Table 54: OUTPUTEN1 - output enable 1 register (address 18h) bit description ...

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Philips Semiconductors Table 56: OUTPUTEN2 - output enable 2 register (address 19h) bit description Bit Symbol 5 DEOENRGB 4 HSOENRGB 3 HPDOEN 2 VSOENRGB 1 CLPOEN 0 FIELDOEN 9.19 Clock output register Table 57: CLKOUTPUT - clock output register (address ...

Page 37

Philips Semiconductors Table 58: CLKOUTPUT - clock output register (address 1Ah) bit description Bit Symbol 1 OUTOSCILL 0 CKOENRGB 9.20 Internal oscillator register Table 59: INTOSC - internal oscillator register (address 1Bh) bit allocation Bit 7 6 Symbol - - ...

Page 38

Philips Semiconductors Table 62: PWRMGT - power management register (address 1Eh) bit description Bit Symbol 1 STBY 0 DVIRGB 9.22 Read register Table 63: READADDR - read register (address 1Fh) bit allocation Bit 7 Symbol - Reset X Access W ...

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Philips Semiconductors Table 67: SIGN - sign register (read register 1) bit allocation Bit 7 Symbol - Reset X Access R Table 68: SIGN - sign register (read register 1) bit description Bit Symbol POLVS2 ...

Page 40

Philips Semiconductors Table 70: ACTIVITY1 - activity detection 1 register (read register 2) bit description Bit Symbol 7 ACVS2 6 ACVS1 5 ACSOG2 4 ACSOG1 3 ACCHS2 2 ACCHS1 1 ACHS2 0 ACHS1 9.26 Activity detection register 2 Remark: It ...

Page 41

Philips Semiconductors Table 72: ACTIVITY2 - activity detection 2 register (read register 3) bit description Bit Symbol ASD 5 3LEVEL 4 ACFIELD 3 HPDO 2 ACVSSEP 1 ACRXC1 0 ACRXC0 10. Limiting values Table 73: Limiting values ...

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Philips Semiconductors 11. Thermal characteristics Table 74: Thermal Characteristics Symbol Parameter R thermal resistance from junction th(j-a) to ambient R thermal resistance from junction th(j-c) to case 12. Characteristics Table 75: Characteristics unless otherwise specified. amb ...

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Philips Semiconductors Table 75: Characteristics …continued unless otherwise specified. amb Symbol Parameter G full-scale channel-to-channel E(rms) matching (RMS value and B clamp N clamp level accuracy clamp Phase-Locked Loop (PLL); see J long term ...

Page 44

Philips Semiconductors Table 75: Characteristics …continued unless otherwise specified. amb Symbol Parameter Hsync inputs Input pins HSYNC1, HSYNC2, CHSYNC1 and CHSYNC2 t minimum pulse width W(Hsync)(min) t maximum pulse width W(Hsync)(max) SOG inputs Input pins SOGIN1 ...

Page 45

Philips Semiconductors 13. Timing B0, Fig 4. Data timing diagram 9397 750 14984 Product data sheet CKDATA sample N sample N RGB input RGB outputs DATA DATA DEO HSYNCO, CKREFO Rev. 06 ...

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ckdivo ckphi ckrefin possibility to add a clock period with bit SCHCKREFO HSYNCL hcount hsyncin dein ckadco ADC out 1 2 HSYNCL, HBACKL and HDISPL ...

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Philips Semiconductors ckrefin HSYNCO CKREFO DEO CKDATA RGB outputs HSCYNCO, DEO, CKREFO and RGB outputs are referred to the rising edge of ckrefin. CKREFO is LOW during 8 clock pulses. Fig 6. Output format ...

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Philips Semiconductors ckrefin HSYNCO CKREFO DEO CKDATA RGB outputs RGB outputs HSYNCO, DEO, CKREFO and RGB outputs are referred to the rising edge of ckrefin. CKREFO is LOW during 8 clock ...

Page 49

Philips Semiconductors 14. Application information GNDD(TTL CCD(TTL CCD HSYNC2 3 CHSYNC2 4 V CCA(PLL) V CCA 5 HSYNC1 6 CHSYNC1 7 GNDA(PLL GNDA(CPO) 220 PMO 680 pF ...

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Philips Semiconductors 15. Package outline LQFP144: plastic low profile quad flat package; 144 leads; body 1 108 109 pin 1 index 144 DIMENSIONS (mm are the original dimensions) A UNIT ...

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Philips Semiconductors LBGA208: plastic low profile ball grid array package; 208 balls; body 1.05 mm ball A1 index area ...

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Philips Semiconductors 16. Soldering 16.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages ...

Page 53

Philips Semiconductors – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, ...

Page 54

Philips Semiconductors [4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, ...

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Philips Semiconductors 17. Revision history Table 78: Revision history Document ID Release date TDA8754_6 20050616 • Modifications: The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors. • Section ...

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Philips Semiconductors 18. Data sheet status [1] Level Data sheet status Product status I Objective data Development II Preliminary data Qualification III Product data Production [1] Please consult the most recently issued data sheet before initiating or completing a design. ...

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Philips Semiconductors 23. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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