DS1868S-10+ Maxim Integrated Products, DS1868S-10+ Datasheet

IC POT DIGITAL DUAL 10K 16-SOIC

DS1868S-10+

Manufacturer Part Number
DS1868S-10+
Description
IC POT DIGITAL DUAL 10K 16-SOIC
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS1868S-10+

Taps
256
Resistance (ohms)
10K
Number Of Circuits
2
Temperature Coefficient
750 ppm/°C Typical
Memory Type
Volatile
Interface
3-Wire Serial
Voltage - Supply
2.7 V ~ 3.3 V, 4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-SOIC (0.300", 7.5mm Width)
Resistance In Ohms
10K
Number Of Pots
Dual
Taps Per Pot
256
Resistance
10 KOhms
Wiper Memory
Volatile
Digital Interface
Serial (3-Wire)
Operating Supply Voltage
4.5 V to 5.5 V
Supply Current
1 uA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Description/function
Dual Digital Potentiometer Chip
Mounting Style
SMD/SMT
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Tolerance
20 %
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
FEATURES
§ Ultra-lowpower consumption, quiet, pumpless
§ Two digitally controlled, 256-position
§ Serial port provides means for setting and
§ Resistors can be connected in series to
§ 20-pin TSSOP, 16-pin SOIC, and 14-pin DIP
§ Resistive elements are temperature
§ Standard resistance values:
§ +5V or ±3V operation
§ Operating Temperature Range:
DESCRIPTION
The DS1868 Dual Digital Potentiometer Chip consists of two digitally controlled solid-state
potentiometers. Each potentiometer is composed of 256 resistive sections. Between each resistive section
and both ends of the potentiometer are tap points which are accessible to the wiper. The position of the
www.dalsemi.com
design
potentiometers
reading both potentiometers
provide increased total resistance
packages are available.
compensated to 0.3 LSB relative linearity
-
-
-
-
DS1868-10 10 k
DS1868-50 50 k
DS1868-100 100 k
Industrial: -40°C to 85°C
1 of 14
Dual Digital Potentiometer Chip
GND
DNC
DNC
DNC
RST
CLK
PIN ASSIGNMENT
PIN DESCRIPTION
L0, L1
H0, H1
W0, W1
S
DQ
CLK
C
V
GND
NC
V
DNC
*All GND pins must be connected to ground.
W1
RST
GND
H1
V
L1
RST
CLK
OUT
DS1868S 16-Pin SOIC (300-mil)
OUT
W1
CC
B
NC
B
H1
L1
V
B
20-Pin TSSOP (173-mil)
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
- Low End of Resistor
- High End of Resistor
- Wiper Terminal of Resistor
- Stacked Configuration Output
- Serial Port Reset Input
- Serial Port Data Input
- Serial Port Clock Input
- Cascade Port Output
- +5 Volt Supply
- Ground Connections
- No Internal Connection
- Substrate Bias Voltage
- Do Not Connect
20
19
18
17
16
15
14
13
12
11
9
V
NC
S
W0
H0
L0
C
DQ
V
DNC
DNC
S
W0
H0
L0
C
DNC
DQ
CC
OUT
OUT
CC
OUT
OUT
GND
RST
CLK
W1
H1
V
L1
B
14-Pin DIP (300-mil)
1
2
3
4
5
6
7
DS1868
14
13
12
11
10
100899
9
8
V
S
W0
H0
L0
C
DQ
CC
OUT
OUT

Related parts for DS1868S-10+

DS1868S-10+ Summary of contents

Page 1

... RST CLK OUT GND DS1868S 16-Pin SOIC (300-mil) PIN DESCRIPTION L0 Low End of Resistor H0 High End of Resistor W0 Wiper Terminal of Resistor S - Stacked Configuration Output OUT - Serial Port Reset Input RST DQ - Serial Port Data Input CLK - Serial Port Clock Input C - Cascade Port Output OUT ...

Page 2

Communication and control of the device is accomplished via a 3-wire serial port interface. This interface allows the ...

Page 3

DS1868 BLOCK DIAGRAM Figure 1 I/O SHIFT REGISTER Figure 2 Transmission of data always begins with the stack select bit followed by the potentiometer-1 wiper position value and lastly the potentiometer-0 wiper position value. When wiper position data is to ...

Page 4

If the stack select bit has value 1, the multiplexed output, S potentiometer-1 wiper DS1868 , will be that of the OUT ...

Page 5

... CASCADE OPERATION A feature of the DS1868 is the ability to control multiple devices from a single processor. Multiple DS1868s can be linked or daisy chained as shown in Figure data bit is entered into the I/O shift register of the DS1868 a bit will appear at the C stack select bit of the DS1868 will always be the first out the part at the beginning of a transaction. The ...

Page 6

ABSOLUTE AND RELATIVE LINEARITY Absolute linearity is defined as the difference between the actual measured output voltage and the expected output voltage. Figure 5 presents the test circuit used to measure absolute linearity. Absolute linearity is given in terms of ...

Page 7

DS1868 ABSOLUTE AND RELATIVE LINEARITY Figure 6 TYPICAL APPLICATION CONFIGURATIONS Figures 7 and 8 show two typical application configurations for the DS1868. By connecting the wiper terminal of the part to a high impedance load, the effects of the wiper ...

Page 8

VARIABLE GAIN AMPLIFIER Figure 7 FIXED GAIN ATTENUATOR Figure DS1868 ...

Page 9

ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground (V Voltage on Any Pin when V =-3.3V B Operating Temperature Storage Temperature Soldering Temperature * This is a stress rating only and functional operation of the device at these ...

Page 10

DS1868 ...

Page 11

CAPACITANCE PARAMETER Input Capacitance Output Capacitance AC ELECTRICAL CHARACTERISTICS PARAMETER CLK Frequency Width of CLK Pulse Data Setup Time Data Hold Time Propagation Delay Time Low to High Level Clock to Output Propagation Delay Time High to Low Level High ...

Page 12

TIMING DIAGRAMS Figure 9 (a) 3-Wire Serial Interface General Overview (b) Start of Communication Transaction (c) End of Communication Transaction DS1868 ...

Page 13

DIGITAL OUTPUT LOAD SCHEMATIC Figure 10 TYPICAL SUPPLY CURRENT VS. SERIAL CLOCK RATE Figure DS1868 ...

Page 14

DS1868 20-PIN TSSOP DIM MIN MAX 1. 0. 0.75 1. 0.09 0. 0.50 0. 0.65 BSC B MM 0.18 0. 6.40 6. ...

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