MCP4332-503E/ST

Manufacturer Part NumberMCP4332-503E/ST
DescriptionIC DGTL POT QUAD 50K 14TSSOP
ManufacturerMicrochip Technology
MCP4332-503E/ST datasheet
 


Specifications of MCP4332-503E/ST

Taps129Resistance (ohms)50K
Number Of Circuits4Temperature Coefficient150 ppm/°C Typical
Memory TypeVolatileInterfaceSPI Serial
Voltage - Supply1.8 V ~ 5.5 VOperating Temperature-40°C ~ 125°C
Mounting TypeSurface MountPackage / Case14-TSSOP
Resistance In Ohms50KLead Free Status / RoHS StatusLead free / RoHS Compliant
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Page 53/88

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7.2
Data Byte
Only the Read command and the Write command use
the data byte, see
Figure
7-1. These commands
concatenate the 8 bits of the data byte with the one
data bit (D8) contained in the command byte to form
9-bits of data (D8:D0). The command byte format
supports up to 9-bits of data so that the 8-bit resistor
network can be set to full scale (100h or greater). This
allows wiper connections to Terminal A and to
Terminal B.
The D9 bit is currently unused, and corresponds to the
position on the SDO data of the CMDERR bit.
7.3
Error Condition
The CMDERR bit indicates if the four address bits
received (AD3:AD0) and the two command bits
received (C1:C0) are a valid combination (see
Table
4-2). The CMDERR bit is high if the combination
is valid and low if the combination is invalid.
The command error bit will also be low if a write to a
nonvolatile address has been specified and another
SPI command occurs before the CS pin is driven
inactive (V
).
IH
SPI commands that do not have a multiple of 8 clocks
are ignored.
Once an error condition has occurred, any following
commands are ignored. All following SDO bits will be
low until the CMDERR condition is cleared by forcing
the CS pin to the inactive state (V
).
IH
 2010 Microchip Technology Inc.
MCP433X/435X
7.3.1
ABORTING A TRANSMISSION
All SPI transmissions must have the correct number of
SCK pulses to be executed. The command is not
executed until the complete number of clocks have
been received. Some commands also require the CS
pin to be forced inactive (V
). If the CS pin is forced to
IH
the inactive state (V
) the serial interface is reset.
IH
Partial commands are not executed.
SPI is more susceptible to noise than other bus
protocols. The most likely case is that this noise
corrupts the value of the data being clocked into the
MCP43XX or the SCK pin is injected with extra clock
pulses. This may cause data to be corrupted in the
device, or a command error to occur, since the address
and command bits were not a valid combination. The
extra SCK pulse will also cause the SPI data (SDI) and
clock (SCK) to be out of sync. Forcing the CS pin to the
inactive state (V
) resets the serial interface. The SPI
IH
interface will ignore activity on the SDI and SCK pins
until the CS pin transition to the active state is detected
(V
to V
or V
to V
).
IH
IL
IH
IHH
Note 1: When data is not being received by the
MCP43XX, It is recommended that the
CS pin be forced to the inactive level (V
2: It is also recommended that long
continuous command strings should be
broken down into single commands or
shorter continuous command strings.
This reduces the probability of noise on
the SCK pin corrupting the desired SPI
commands.
DS22242A-page 53
)
IL