IC DGTL POT 8BIT 1K 1CH 8-SOIC

AD8400AR1

Manufacturer Part NumberAD8400AR1
DescriptionIC DGTL POT 8BIT 1K 1CH 8-SOIC
ManufacturerAnalog Devices Inc
AD8400AR1 datasheet
 

Specifications of AD8400AR1

Rohs StatusRoHS non-compliantTaps256
Resistance (ohms)1KNumber Of Circuits1
Temperature Coefficient500 ppm/°C TypicalMemory TypeVolatile
InterfaceSPI, 3-Wire SerialVoltage - Supply2.7 V ~ 5.5 V
Operating Temperature-40°C ~ 125°CMounting TypeSurface Mount
Package / Case8-SOIC (3.9mm Width)Resistance In Ohms1.00K
End To End Resistance1kohmTrack TaperLinear
No. Of Steps256Resistance Tolerance± 33%
Supply Voltage Range2.7V To 5.5VControl InterfaceSerial, SPI
No. Of PotsSingle  
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AD8400/AD8402/AD8403
CS
CLK
D7
EN
RDAC
LATCH
NO. 1
ADDR
R
A1
DEC
D0
DO
SDO
A0
D7
SER
AD8403
REG
D7
SDI
DI
D0
RDAC
LATCH
NO. 4
R
8
D0
SHDN
DGND
RS
Figure 48. AD8403 Block Diagram
Table 12. Input Logic Control Truth Table
CLK
CS
RS
SHDN
Register Activity
L
L
H
H
No SR effect; enables SDO pin
P
L
H
H
Shift one bit in from the SDI pin. The
10th previously entered bit is shifted
out of the SDO pin.
X
P
H
H
Load SR data into RDAC latch based
on A1, A0 decode (Table 13).
X
H
H
H
No operation
X
X
L
H
Sets all RDAC latches to midscale,
wiper centered, and SDO latch
cleared
X
H
P
H
Latches all RDAC latches to 80
X
H
H
L
Open-circuits all Resistor A terminals,
connects W to B, turns off SDO
output transistor.
1
P = positive edge, X = don’t care, SR = shift register
The serial data output (SDO) pin, which exists only on the
AD8403 and not on the AD8400 or AD8402, contains an
open-drain, n-channel FET that requires a pull-up resistor to
transfer data to the SDI pin of the next package. The pull-up
resistor termination voltage may be larger than the V
(but less than the max V
of 8 V) of the AD8403 SDO output
DD
device. For example, the AD8403 could operate at V
and the pull-up for interface to the next device could be set at 5 V.
This allows for daisy-chaining several RDACs from a single proc-
essor serial data line. The clock period needs to be increased
when using a pull-up resistor to the SDI pin of the following
device in the series. Capacitive loading at the daisy-chain node
SDO to SDI between devices must be accounted for in order to
transfer data successfully. When daisy chain is used, CS should
be kept low until all the bits of every package are clocked into
their respective serial registers and the address and data bits are
in the proper decoding location.
If two AD8403 RDACs are daisy-chained, it requires 20 bits
V
DD
of address and data in the format shown in Table 6. During
A1
shutdown ( SHDN = logic low), the SDO output pin is forced
W1
to the off (logic high) state to disable power dissipation in the
B1
pull-up resistor. See
schematic.
The data setup and hold times in the specification table deter-
mine the data valid time requirements. The last 10 bits of the
data-word entered into the serial register are held when CS
returns high. At the same time CS goes high it gates the address
A4
decoder, which enables one of the two (AD8402) or four (AD8403)
W4
positive edge-triggered RDAC latches. See
B4
Table 13. Address Decode Table
A1
0
AGND
0
1
1
1
The target RDAC latch is loaded with the last eight bits of the
serial data-word completing one RDAC update. In the case of
H
AD8403, four separate 10-bit data-words must be clocked in to
change all four VR settings.
supply
DD
= 3.3 V,
All digital pins are protected with a series input resistor and
DD
parallel Zener ESD structure shown in Figure 51. This structure
applies to digital pins CS , SDI, SDO, RS , SHDN , and CLK. The
digital input ESD protection allows for mixed power supply
applications where 5 V CMOS logic can be used to drive an
AD8400, AD8402, or AD8403 operating from a 3 V power
supply. Analog Pin A, Pin B, and Pin W are protected with a
20 Ω series resistor and parallel Zener diode (see
Rev. E | Page 22 of 32
Figure 50
for equivalent SDO output circuit
Figure 49
A0
Latch Decoded
0
RDAC#1
1
RDAC#2
0
RDAC#3 AD8403 Only
1
RDAC#4 AD8403 Only
AD8403
RDAC 1
RDAC 2
CS
ADDR
DECODE
RDAC 4
CLK
SERIAL
REGISTER
SDI
Figure 49. Equivalent Input Control Logic
SHDN
CS
SERIAL
D
Q
SDI
REGISTER
CK RS
CLK
RS
Figure 50. Detailed SDO Output Schematic of the AD8403
and
Table 13
.
SDO
Figure 52
).