IC DGTL POT 8BIT 1K 1CH 8-SOIC

AD8400AR1

Manufacturer Part NumberAD8400AR1
DescriptionIC DGTL POT 8BIT 1K 1CH 8-SOIC
ManufacturerAnalog Devices Inc
AD8400AR1 datasheet
 


Specifications of AD8400AR1

Rohs StatusRoHS non-compliantTaps256
Resistance (ohms)1KNumber Of Circuits1
Temperature Coefficient500 ppm/°C TypicalMemory TypeVolatile
InterfaceSPI, 3-Wire SerialVoltage - Supply2.7 V ~ 5.5 V
Operating Temperature-40°C ~ 125°CMounting TypeSurface Mount
Package / Case8-SOIC (3.9mm Width)Resistance In Ohms1.00K
End To End Resistance1kohmTrack TaperLinear
No. Of Steps256Resistance Tolerance± 33%
Supply Voltage Range2.7V To 5.5VControl InterfaceSerial, SPI
No. Of PotsSingle  
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Parameter
Symbol
6, 10
DYNAMIC CHARACTERISTICS
Bandwidth −3 dB
BW_50 K
BW_100 K
Total Harmonic Distortion
THD
V
Settling Time
t
_50 K
W
S
t
_100 K
S
Resistor Noise Voltage
e
NWB
e
NWB
11
Crosstalk
C
T
1
Typicals represent average readings at 25°C and V
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See the test circuit in Figure 38.
I
= V
/R for V
= 3 V or 5 V for the 50 kΩ and 100 kΩ versions.
W
DD
DD
3
V
= V
, wiper (V
) = no connect.
AB
DD
W
4
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See the test circuit in Figure 37.
5
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.
7
Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode.
8
Worst-case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See Figure 28 for a plot of I
9
P
is calculated from (I
× V
). CMOS logic level inputs result in minimum power dissipation.
DISS
DD
DD
10
All dynamic characteristics use V
= 5 V.
DD
11
Measured at a V
pin where an adjacent V
pin is making a full-scale voltage change.
W
W
Conditions
R = 50 kΩ
R = 100 kΩ
V
= 1 V rms + 2 V dc, V
= 2 V dc, f = 1 kHz
W
A
B
V
= V
, V
= 0 V, ±1% error band
A
DD
B
V
= V
, V
= 0 V, ±1% error band
A
DD
B
_50 K
= 25 kΩ, f = 1 kHz, RS = 0
R
WB
_100 K
= 50 kΩ, f = 1 kHz, RS = 0
R
WB
V
= V
, V
= 0 V
A
DD
B
= 5 V.
DD
Rev. E | Page 7 of 32
AD8400/AD8402/AD8403
1
Min
Typ
Max
Unit
125
kHz
71
kHz
0.003
%
9
μs
18
μs
20
nV/√Hz
29
nV/√Hz
−65
dB
= V
and V
= 0 V.
A
DD
B
vs. logic voltage.
DD