AD5233BRUZ10-R7 Analog Devices Inc, AD5233BRUZ10-R7 Datasheet - Page 18

IC DGTL POT QUAD 64POS 24-TSSOP

AD5233BRUZ10-R7

Manufacturer Part Number
AD5233BRUZ10-R7
Description
IC DGTL POT QUAD 64POS 24-TSSOP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD5233BRUZ10-R7

Taps
64
Resistance (ohms)
10K
Number Of Circuits
4
Temperature Coefficient
600 ppm/°C Typical
Memory Type
Non-Volatile
Interface
4-Wire SPI Serial
Voltage - Supply
2.7 V ~ 5.5 V, ±2.25 V ~ 2.75 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-TSSOP
Resistance In Ohms
10K
Number Of Elements
4
# Of Taps
64
Resistance (max)
10KOhm
Power Supply Requirement
Single/Dual
Interface Type
Serial (4-Wire/SPI)
Single Supply Voltage (typ)
3/5V
Dual Supply Voltage (typ)
±2.5V
Single Supply Voltage (min)
2.7V
Single Supply Voltage (max)
5.5V
Dual Supply Voltage (min)
±2.25V
Dual Supply Voltage (max)
±2.75V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
24
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
AD5233
In Table 6, C0 to C3 are command bits, A3 to A0 are address bits, D0 to D5 are data bits that are applicable to the RDAC wiper register,
and D0 to D7 are applicable to the EEMEM register.
Table 6. 16-Bit Serial Data-Word
MSB
RDAC
EEMEM
Command instruction codes are defined in Table 7.
Table 7. Instruction/Operation Truth Table
Inst.
No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
2
3
4
5
4
5
5
5
5
The SDO output shifts out the last 16 bits of data clocked into the serial register for daisy-chain operation. Exception: for any instruction following Instruction 9 or
Instruction 10, see details of these instructions for proper usage.
The RDAC register is a volatile scratchpad register that is automatically refreshed at power-on from the corresponding nonvolatile EEMEM register.
Execution of these operations takes place when the CS strobe returns to Logic 1.
Instruction 3 writes one data byte (eight bits of data) to EEMEM. In the case of Address 0, Address 1, Address 2, and Address 3, only the last six bits are valid for wiper
position setting.
The increment, decrement, and shift instructions ignore the contents of the Shift Register Data Byte 0.
5
5
5
5
Instruction Byte 0
B16
C3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Instruction Byte
C3
C3
C2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
C2
C2
C0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
C1
C1
A3
0
0
A3
0
X
0
X
A3
0
0
0
X
0
X
X
X
C0
A2
X
0
0
A2
0
X
0
X
X
A2
0
0
0
X
0
X
C0
A1
X
A1
A1
A1
A1
X
A1
X
X
A1
A1
A1
A1
X
A1
X
0
A3
1, 2, 3
B8
A0
X
A0
A0
A0
A0
X
A0
X
X
A0
A0
A0
A0
X
A0
X
0
A2
B7
Data Byte 0
D7
X
X
X
D7
X
X
X
X
X
X
X
X
X
X
X
X
B6
D6
X
X
X
D6
X
X
X
X
X
X
X
X
X
X
X
X
A1
A1
Rev. B | Page 18 of 32
B5
D5
X
X
X
D5
X
X
X
X
X
X
X
X
X
D5
X
X
LSB
A0
A0
B4
D4
X
X
X
D4
X
X
X
X
X
X
X
D4
X
X
X
X
Data Byte
X
D7
B3
D3
X
X
X
D3
X
X
X
X
X
X
X
D3
X
X
X
X
X
D6
B2
D2
X
X
X
D2
X
X
X
X
X
X
X
D2
X
X
X
X
B1
D1
X
X
X
D1
X
X
X
X
X
X
X
D1
X
X
X
X
D5
D5
B0
D0
X
D0
X
D0
X
X
X
X
X
X
X
X
X
X
X
X
D4
D4
Operation
NOP: Do nothing. See Table 14 for
programming example.
Restore EEMEM contents to the RDAC
register. This command leaves the device
in read program power state. To return
the part to the idle state, perform NOP
instruction 0. See Table 14.
Store wiper setting: Store RDAC (ADDR)
setting to EEMEM. See Table 13.
Store contents of Serial Register Data
Byte 0 (total eight bits) to EEMEM
(ADDR). See Table 16.
Decrement 6 dB: right-shift contents of
RDAC register, stop at all 0s.
Decrement all 6 dB: right-shift contents
of all RDAC registers, stop at all 0s.
Decrement content of RDAC register
by 1, stop at all 0s.
Decrement contents of all the RDAC
registers by 1, stop at all 0s.
Reset: refresh all RDACs with their
corresponding EEMEM previously
stored values.
Read content of EEMEM (ADDR) from
SDO output in the next frame. See
Table 17.
Read RDAC wiper setting from SDO
output in the next frame. See Table 18.
Write contents of Serial Register Data
Byte 0 (total six bits) to RDAC. See
Table 12.
Increment 6 dB: Left-shift contents of
RDAC register, stop at all 1s. See
Table 15.
Increment all 6 dB: left-shift contents of
RDAC registers, stop at all 1s.
Increment contents of the RDAC
register by 1, stop at all 1s. See
Table 13.
Increment contents of all RDAC
registers by 1, stop at all 1s.
D3
D3
D2
D2
D1
D1
D0
D0

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