AD5233BRUZ10-R7 Analog Devices Inc, AD5233BRUZ10-R7 Datasheet - Page 19

IC DGTL POT QUAD 64POS 24-TSSOP

AD5233BRUZ10-R7

Manufacturer Part Number
AD5233BRUZ10-R7
Description
IC DGTL POT QUAD 64POS 24-TSSOP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD5233BRUZ10-R7

Taps
64
Resistance (ohms)
10K
Number Of Circuits
4
Temperature Coefficient
600 ppm/°C Typical
Memory Type
Non-Volatile
Interface
4-Wire SPI Serial
Voltage - Supply
2.7 V ~ 5.5 V, ±2.25 V ~ 2.75 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-TSSOP
Resistance In Ohms
10K
Number Of Elements
4
# Of Taps
64
Resistance (max)
10KOhm
Power Supply Requirement
Single/Dual
Interface Type
Serial (4-Wire/SPI)
Single Supply Voltage (typ)
3/5V
Dual Supply Voltage (typ)
±2.5V
Single Supply Voltage (min)
2.7V
Single Supply Voltage (max)
5.5V
Dual Supply Voltage (min)
±2.25V
Dual Supply Voltage (max)
±2.75V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
24
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ADVANCED CONTROL MODES
The AD5233 digital potentiometer includes a set of user
programming features to address the wide number of
applications for these universal adjustment devices.
Key programming features include
Linear Increment and Decrement Instructions
The increment and decrement instructions (14, 15, 6, and 7)
are useful for linear step-adjustment applications. These com-
mands simplify microcontroller software coding by allowing the
controller to send just an increment or decrement command to
the device.
For an increment command, executing Instruction 14 with
the proper address automatically moves the wiper to the next
resistance segment position. Instruction 15 performs the same
function, except that the address does not need to be specified.
All RDACs are changed at the same time.
Logarithmic Taper Mode Adjustment
Four programming instructions produce logarithmic taper
increment and decrement of the wiper. These settings are
activated by the 6 dB increment and 6 dB decrement instruc-
tions (12, 13, 4, and 5). For example, starting at zero scale,
executing the increment Instruction 12 seven times moves
the wiper in 6 dB per step from 0% to full scale, R
increment instruction doubles the value of the RDAC register
contents each time the command is executed. When the wiper
position is near the maximum setting, the last 6 dB increment
instruction causes the wiper to go to the full-scale 63
position. Further 6 dB per increment instructions do not
change the wiper position beyond its full scale.
The 6 dB step increments and 6 dB step decrements are achieved
by shifting the bit internally to the left or right, respectively.
The following information explains the nonideal ±6 dB step
adjustment under certain conditions. Table 8 illustrates the
operation of the shifting function on the RDAC register data
bits. Each table row represents a successive shift operation.
Note that the left-shift 12 and 13 instructions were modified
such that, if the data in the RDAC register is equal to zero and
the data is shifted left, the RDAC register is then set to Code 1.
Similarly, if the data in the RDAC register is greater than or
equal to midscale and the data is shifted left, then the
Scratchpad programming to any desirable values
Nonvolatile memory storage of the scratchpad RDAC
register value in the EEMEM register
Increment and decrement instructions for the RDAC
wiper register
Left- and right-bit shift of the RDAC wiper register to
achieve ±6 dB level changes
Eleven extra bytes of user-addressable nonvolatile memory
AB
. The 6 dB
10
code
Rev. B | Page 19 of 32
data in the RDAC register is automatically set to full scale. This
makes the left-shift function as ideal a logarithmic adjustment
as possible.
The right-shift 4 and 5 instructions are ideal only if the LSB is
0 (ideal logarithmic = no error). If the LSB is a 1, the right-shift
function generates a linear half-LSB error, which translates to
a number-of-bits-dependent logarithmic error, as shown in
Figure 42. The plot shows the error of the odd numbers of bits
for the AD5233.
Table 8. Detail Left-Shift and Right-Shift Functions for
6 dB Step Increment and Decrement
Left-Shift
(+6 dB/Step)
00 0000
00 0001
00 0010
00 0100
00 1000
01 0000
10 0000
11 1111
11 1111
Actual conformance to a logarithmic curve between the data
contents in the RDAC register and the wiper position for each
right-shift 4 and 5 command execution contains an error only
for odd numbers of bits. Even numbers of bits are ideal. The
graph in Figure 42 shows plots of log error [20 × log
code)] for the AD5233. For example, Code 3 log error = 20 ×
log
plot of log error is more significant at the lower codes.
Figure 42. Plot of Log Error Conformance for Odd Numbers of Bits Only (Even
10
(0.5/3) = −15.56 dB, which is the worst-case scenario. The
–10
–20
–30
–40
–50
0
0
5
10
–15.56dB @ CODE 3
15
Numbers of Bits are Ideal)
20
25
CODE (Decimal)
30
Right-Shift
(–6 dB/Step)
11 1111
01 1111
00 1111
00 0111
00 0011
00 0001
00 0000
00 0000
00 0000
35
40
45 50
55
AD5233
10
60
(error/
65

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