IC POT DIG QUAD 100K 8B 24TSSOP

AD8403ARU100-REEL

Manufacturer Part NumberAD8403ARU100-REEL
DescriptionIC POT DIG QUAD 100K 8B 24TSSOP
ManufacturerAnalog Devices Inc
AD8403ARU100-REEL datasheet
 


Specifications of AD8403ARU100-REEL

Rohs StatusRoHS non-compliantTaps256
Resistance (ohms)100KNumber Of Circuits4
Temperature Coefficient500 ppm/°C TypicalMemory TypeVolatile
InterfaceSPI, 3-Wire SerialVoltage - Supply2.7 V ~ 5.5 V
Operating Temperature-40°C ~ 125°CMounting TypeSurface Mount
Package / Case24-TSSOPResistance In Ohms100K
Number Of Elements4# Of Taps256
Resistance (max)100KOhmPower Supply RequirementSingle
Interface TypeSerial (3-Wire/SPI)Single Supply Voltage (typ)3/5V
Dual Supply Voltage (typ)Not RequiredVSingle Supply Voltage (min)2.7V
Single Supply Voltage (max)5.5VDual Supply Voltage (min)Not RequiredV
Dual Supply Voltage (max)Not RequiredVOperating Temp Range-40C to 125C
Operating Temperature ClassificationAutomotiveMountingSurface Mount
Pin Count24Package TypeTSSOP
For Use WithAD8403EVAL - BOARD EVAL FOR AD8403  
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AD8400/AD8402/AD8403
ELECTRICAL CHARACTERISTICS—ALL VERSIONS
V
= 3 V ± 10% or 5 V ± 10%, V
= V
DD
A
DD
Table 4.
Parameter
SWITCHING CHARACTERISTICS
2, 3
Input Clock Pulse Width
Data Setup Time
Data Hold Time
4
CLK to SDO Propagation Delay
CS Setup Time
CS High Pulse Width
Reset Pulse Width
CLK Fall to CS Rise Hold Time
CS Rise to Clock Rise Setup
1
Typicals represent average readings at 25°C and V
2
Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal.
The remaining resistor terminals are left open circuit.
3
See the timing diagram in Figure 3 for location of measured values. All input control voltages are specified with t
timed from a voltage level of 1.6 V. Switching characteristics are measured using V
of 1 V/μs should be maintained.
4
Propagation delay depends on the value of V
DD
TIMING DIAGRAMS
1
A1
A0
D7
D6
D5
D4
D3
D2
D1
SDI
0
1
CLK
0
DAC REGISTER LOAD
1
CS
0
V
DD
V
OUT
0V
Figure 3. Timing Diagram
1
SDI
Ax OR Dx
Ax OR Dx
(DATA IN)
0
t
DS
t
DH
1
SDO
A'x OR D'x
A'x OR D'x
(DATA OUT)
0
t
PD_MIN
t
CH
1
CLK
0
t
CL
t
1
CSS
CS
0
V
DD
V
OUT
0V
Figure 4. Detailed Timing Diagram
, V
= 0 V, −40°C ≤ T
≤ +125°C, unless otherwise noted.
B
A
Symbol
Conditions
t
, t
Clock level high or low
CH
CL
t
DS
t
DH
t
R
= 1 kΩ to 5 V, C
PD
L
t
CSS
t
CSW
t
RS
t
CSH
t
CS1
= 5 V.
DD
= 3 V or 5 V. To avoid false clocking, a minimum input logic slew rate
DD
, R
, and C
(see the Applications section).
L
L
D0
t
PD_MAX
t
CS1
t
CSH
t
CSW
t
S
±1%
±1% ERROR BAND
Rev. E | Page 10 of 32
1
Min
Typ
10
5
5
≤ 20 pF
1
L
10
10
50
0
10
= t
= 1 ns (10% to 90% of V
) and
R
F
DD
t
RS
1
RS
0
t
S
V
DD
V
±1%
OUT
V
/2
±1% ERROR BAND
DD
Figure 5. Reset Timing Diagram
Max
Unit
ns
ns
ns
25
ns
ns
ns
ns
ns
ns