AD5231BRU10 Analog Devices Inc, AD5231BRU10 Datasheet - Page 15

• Manufacturer Part Number: AD5231BRU10
• Description: IC DGTL POT 1024POS 16-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5231BRU10

• Rohs Status: RoHS non-compliant
• Taps: 1024
• Resistance (ohms): 10K
• Number Of Circuits: 1
• Temperature Coefficient: 600 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: 4-Wire SPI Serial
• Voltage - Supply: 2.7 V ~ 5.5 V, ±2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resistance In Ohms: 10K
• End To End Resistance: 10kohm
• Track Taper: Logarithmic
• Resistance Tolerance: +20, -40%
• No. Of Steps: 1024
• Supply Voltage Range: 2.7V To 5.5V, ± 2.25V To ± 2.75V
• Control Interface: Serial, SPI
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DIGITAL INPUT/OUTPUT CONFIGURATION
All digital inputs are ESD-protected, high input impedance that
can be driven directly from most digital sources. Active at logic
low, PR and WP must be tied to V
internal pull-up resistors are present on any digital input pins.
The SDO and RDY pins are open-drain digital outputs that
need pull-up resistors only if these functions are used. A resistor
value in the range of 1 kΩ to 10 kΩ is a proper choice that
balances the dissipation and switching speed.
The equivalent serial data input and output logic is shown in
Figure 36. The open-drain output SDO is disabled whenever
chip-select CS is in logic high. ESD protection of the digital
inputs is shown in Figure 37 and Figure 38.
SERIAL DATA INTERFACE
The AD5231 contains a 4-wire SPI-compatible digital interface
(SDI, SDO, CS , and CLK). It uses a 24-bit serial data-word
loaded MSB first. The format of the SPI-compatible word is
shown in Table 6. The chip-select CS pin must be held low until
the complete data-word is loaded into the SDI pin. When CS
CLK
SDI
CS
Figure 37. Equivalent ESD Digital Input Protection
Figure 36. Equivalent Digital Input-Output Logic
LOGIC
PINS
WP
Figure 38. Equivalent WP Input Protection
COUNTER
COMMAND
VALID
INPUT
300Ω
REGISTER
SERIAL
INPUT
300Ω
AND ADDRESS
AD5231
PROCESSOR
PR
COMMAND
DECODE
DD
if they are not used. No
GND
WP
V
DD
GND
V
DD
SDO
GND
5V
R
PULL-UP
Rev. C | Page 15 of 28
returns high, the serial data-word is decoded according to the
instructions in Table 7. The command bits (Cx) control the
operation of the digital potentiometer. The address bits (Ax)
determine which register is activated. The data bits (Dx) are the
values that are loaded into the decoded register.
The AD5231 has an internal counter that counts a multiple of
24 bits (a frame) for proper operation. For example, AD5231
works with a 48-bit word, but it cannot work properly with a
23-bit or 25-bit word. In addition, AD5231 has a subtle feature
that, if CS is pulsed without CLK and SDI, the part repeats the
previous command (except during power-up). As a result, care
must be taken to ensure that no excessive noise exists in the
CLK or CS line that might alter the effective number of bits
(ENOB) pattern. Also, to prevent data from mislocking (due
to noise, for example), the counter resets if the count is not a
multiple of four when CS goes high.
The SPI interface can be used in two slave modes: CPHA = 1,
CPOL = 1 and CPHA = 0, CPOL = 0. CPHA and CPOL refer to
the control bits that dictate SPI timing in the following
MicroConverters® and microprocessors: ADuC812/ADuC824,
M68HC11, and MC68HC16R1/916R1.
DAISY-CHAIN OPERATION
The serial data output pin (SDO) serves two purposes. It can be
used to read the contents of the wiper setting and EEMEM
values using Instruction 10 and Instruction 9, respectively. The
remaining instructions (0 to 8, 11 to 15) are valid for daisy-
chaining multiple devices in simultaneous operations. Daisy-
chaining minimizes the number of port pins required from
the controlling IC (see Figure 39). The SDO pin contains an
open-drain N-Ch FET that requires a pull-up resistor if this
function is used. As shown in Figure 39, users need to tie the
SDO pin of one package to the SDI pin of the next package.
Users might need to increase the clock period, because the
pull-up resistor and the capacitive loading at the SDO to SDI
interface might require additional time delay between sub-
sequent packages. When two AD5231s are daisy-chained,
48 bits of data are required. The first 24 bits go to U2 and the
second 24 bits go to U1. The CS should be kept low until all
48 bits are clocked into their respective serial registers. The CS
is then pulled high to complete the operation.
µC
Figure 39. Daisy-Chain Configuration Using SDO
SDI
CS
AD5231
U1
CLK
SDO
+V
R
2kΩ
P
SDI
CS
AD5231
U2
CLK
AD5231
SDO