AD5232BRU10 Analog Devices Inc, AD5232BRU10 Datasheet - Page 5

• Manufacturer Part Number: AD5232BRU10
• Description: IC DGTL POT DUAL 256POS 16-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5232BRU10

• Rohs Status: RoHS non-compliant
• Taps: 256
• Resistance (ohms): 10K
• Number Of Circuits: 2
• Temperature Coefficient: 600 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: 4-Wire SPI Serial
• Voltage - Supply: 2.7 V ~ 5.5 V, ±2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resistance In Ohms: 10K
• End To End Resistance: 10kohm
• Track Taper: Linear / Logarithmic
• Resistance Tolerance: +20, -40%
• No. Of Steps: 256
• Supply Voltage Range: 2.7V To 5.5V, ± 2.25V To ± 2.75V
• Number Of Elements: 2
• # Of Taps: 256
• Resistance (max): 10KOhm
• Power Supply Requirement: Single/Dual
• Interface Type: Serial (4-Wire/SPI)
• Single Supply Voltage (typ): 3/5V
• Dual Supply Voltage (typ): ±2.5V
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): ±2.25V
• Dual Supply Voltage (max): ±2.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Package Type: TSSOP
• For Use With: EVAL-AD5232-10EBZ - BOARD EVALUATION FOR AD5232-10
• Lead Free Status / Rohs Status: Not Compliant

INTERFACE TIMING CHARACTERISTICS
All input control voltages are specified with t
characteristics are measured using both V
Table 2.
Parameter
Clock Cycle Time (t
CS Setup Time
CLK Shutdown Time to CS Rise
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CS to SDO-SPI Line Acquire
CS to SDO-SPI Line Release
CLK to SDO Propagation Delay
CLK to SDO Data Hold Time
CS High Pulse Width
CS High to CS High
RDY Rise to CS Fall
CS Rise to RDY Fall Time
Store/Read EEMEM Time
CS Rise to Clock Rise/Fall Setup
Preset Pulse Width (Asynchronous)
Preset Response Time to RDY High
1
2
3
4
5
6
Guaranteed by design; not subject to production test.
See the Timing Diagrams section for the location of measured values.
Typicals represent average readings at 25°C and V
Propagation delay depends on the value of V
Valid for commands that do not activate the RDY pin.
RDY pin low only for Command Instruction 2, Command Instruction 3, Command Instruction 8, Command Instruction 9, Command Instruction 10, and the PR hardware pulse:
CMD_8 ~ 1 ms, CMD_9 = CMD_10 ~ 0.12 ms, and CMD_2 = CMD_3 ~ 20 ms. Device operation at T
1, 2
CYC
5
5
)
6
4
DD
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
, R
1
2
3
4
6
7
8
9
10
11
12
13
14
15
16
17
PRW
PRESP
, t
PULL-UP
DD
DD
5
= 5 V.
= 3 V and V
R
, and C
= t
F
= 2.5 ns (10% to 90% of 3 V) and are timed from a voltage level of 1.5 V. Switching
Conditions
Clock level high or low
From positive CLK transition
From positive CLK transition
R
R
Applies to Command Instruction 2, Command
Instruction 3, and Command Instruction 9
Not shown in timing diagram
PR pulsed low to refresh wiper positions
L
.
P
P
= 2.2 kΩ, C
= 2.2 kΩ, C
DD
= 5 V.
Rev. A | Page 5 of 24
L
L
< 20 pF
< 20 pF
A
= −40°C and V
DD
< 3 V extends the save time to 35 ms.
Min
20
10
1
10
5
5
0
10
4
0
10
50
Typ
0.15
70
3
Max
40
50
50
0.3
25
AD5232
Unit
ns
ns
t
ns
ns
ns
ns
ns
ns
ns
ns
t
ns
ms
ms
ns
ns
μs
CYC
CYC