AD8403ARUZ1 Analog Devices Inc, AD8403ARUZ1 Datasheet - Page 5

IC POT DGTL QUAD 1K 24-TSSOP

AD8403ARUZ1

Manufacturer Part Number
AD8403ARUZ1
Description
IC POT DGTL QUAD 1K 24-TSSOP
Manufacturer
Analog Devices Inc
Datasheets

Specifications of AD8403ARUZ1

Temperature Coefficient
500 ppm/°C Typical
Taps
256
Resistance (ohms)
1K
Number Of Circuits
4
Memory Type
Volatile
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
24-TSSOP
Resistance In Ohms
1.00K
End To End Resistance
1kohm
No. Of Steps
256
Supply Voltage Range
2.7V To 5.5V
Control Interface
Serial, 3-Wire
No. Of Pots
Quad
Potentiometer Ic Case
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD8403EVAL - BOARD EVAL FOR AD8403
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Parameter
DYNAMIC CHARACTERISTICS
1
2
3
4
5
6
7
8
9
10
11
Typical represents average readings at 25°C and V
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See the test circuit in Figure 38.
I
V
INL and DNL are measured at V
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See the test circuit in Figure 37.
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.
Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode.
Worst-case supply current is consumed when the input logic level is at 2.4 V, a standard characteristic of CMOS logic. See Figure 28 for a plot of I
P
W
All dynamic characteristics use V
Measured at a V
AB
DISS
Bandwidth −3 dB
Total Harmonic Distortion
V
Resistor Noise Voltage
Crosstalk
= 50 μA for V
W
= V
is calculated from (I
Settling Time
DD
, wiper (V
11
DD
W
= 3 V and I
W
pin where an adjacent V
) = no connect.
DD
× V
W
DD
= 400 μA for V
W
). CMOS logic level inputs result in minimum power dissipation.
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
DD
6, 10
= 5 V.
W
Symbol
BW_10 K
THD
t
e
C
DD
pin is making a full-scale voltage change.
S
NWB
T
= 5 V for the 10 kΩ versions.
W
DD
= 5 V.
Conditions
R = 10 kΩ
V
V
R
V
A
A
WB
A
= 1 V rms + 2 V dc, V
= V
= V
= 5 kΩ, f = 1 kHz, RS = 0
DD
DD
, V
, V
B
B
Rev. E | Page 5 of 32
= 0 V, ±1% error band
= 0 V
B
= 2 V dc, f = 1 kHz
Min
AD8400/AD8402/AD8403
A
= V
Typ
600
0.003
2
9
−65
DD
and V
1
B
DD
= 0 V.
Max
vs. logic voltage.
Unit
kHz
%
μs
nV/√Hz
dB

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