IC XDCP DUAL 256TAP 50K 24-SOIC

 

X9268US24Z

Manufacturer Part NumberX9268US24Z
DescriptionIC XDCP DUAL 256TAP 50K 24-SOIC
ManufacturerIntersil
SeriesXDCP™
X9268US24Z datasheets

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Specifications of X9268US24Z

Taps256Resistance (ohms)50K
Number Of Circuits2Temperature Coefficient300 ppm/°C Typical
Memory TypeNon-VolatileInterfaceI²C, 2-Wire Serial
Voltage - Supply4.5 V ~ 5.5 VOperating Temperature0°C ~ 70°C
Mounting TypeSurface MountPackage / Case24-SOIC (7.5mm Width)
Resistance In Ohms50KTrack TaperLinear
Resistance Tolerance± 20%No. Of Steps256
Supply Voltage Range4.5V To 5.5VControl Interface2 Wire, Serial
No. Of PotsDualRohs CompliantYes
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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PRINCIPLES OF OPERATION
The X9268 is a integrated microcircuit incorporating
four resistor arrays and their associated registers and
counters and the serial interface logic providing direct
communication between the host and the digitally
controlled potentiometers. This section provides detail
description of the following:
– Resistor Array Description
– Serial Interface Description
– Instruction and Register Description.
Array Description
The X9268 is comprised of a resistor array (See
Figure 1). Each array contains 255 discrete resistive
segments that are connected in series. The physical
ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (R
inputs).
Figure 1. Detailed Potentiometer Block Diagram
One of Two Potentiometers
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
REGISTER 0
(DR0)
REGISTER 2
(DR2)
IF WCR = 00[H] THEN R
= R
W
L
IF WCR = FF[H] THEN R
= R
W
H
6
X9268
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(R
) output. Within each individual array only one
W
switch may be turned on at a time.
These switches are controlled by a Wiper Counter
Register (WCR). The 8-bits of the WCR (WCR[7:0])
are decoded to select, and enable, one of 256
switches (See Table 1).
The WCR may be written directly. These Data
Registers can the WCR can be read and written by the
host system.
Power-up and Down Requirements.
At all times, the voltages on the potentiometer pins
must be less than V+ and more than V-. During power-
up and power-down, V
final values within 1msecs of each other. The V
and R
H
L
ramp rate spec is always in effect.
SERIAL
BUS
INPUT
REGISTER 1
(DR1)
8
8
PARALLEL
BUS
INPUT
REGISTER 3
WIPER
(DR3)
COUNTER
REGISTER
(WCR)
INC/DEC
LOGIC
UP/DN
UP/DN
MODIFIED SCL
CLK
, V+, and V- must reach their
CC
R
H
C
O
U
N
T
E
R
D
E
C
O
D
E
R
L
R
W
FN8172.4
August 29, 2006
CC

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