AD5331BRUZ Analog Devices Inc, AD5331BRUZ Datasheet - Page 8

• Manufacturer Part Number: AD5331BRUZ
• Description: IC DAC 10BIT SNGL VOUT 20TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5331BRUZ

• Data Interface: Parallel
• Settling Time: 7µs
• Number Of Bits: 10
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 1.25mW
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Resolution (bits): 10bit
• Sampling Rate: 143kSPS
• Input Channel Type: Parallel
• Supply Voltage Range - Analog: 2.5V To 5.5V
• Supply Current: 140µA
• Number Of Channels: 1
• Resolution: 10b
• Conversion Rate: 143KSPS
• Interface Type: Parallel
• Single Supply Voltage (typ): 3.3/5V
• Dual Supply Voltage (typ): Not RequiredV
• Architecture: Resistor-String
• Power Supply Requirement: Single
• Output Type: Voltage
• Integral Nonlinearity Error: ±4LSB
• Single Supply Voltage (min): 2.5V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Package Type: TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD5330/AD5331/AD5340/AD5341
Table 6. AD5331 Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13 to 20
LDAC
GAIN
CLR
DB
DB
DB
DB
WR
CS
. .
GAIN
Mnemonic
DB
DB
V
V
GND
CS
WR
CLR
LDAC
PD
V
DB
8
9 2
7
0
REF
OUT
DD
20
13
10
1
8
6
7
9
8
9
0
to DB
7
RESET
Description
Parallel Data Input.
Most Significant Bit of Parallel Data Input.
Unbuffered Reference Input.
Output of DAC. Buffered output with rail-to-rail operation.
Ground reference point for all circuitry on the part.
Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
Gain Control Pin. This controls whether the output range from the DAC is 0 V to V
Active low control input that clears all input registers and DAC registers to zero.
Active low control input that updates the DAC registers with the contents of the input registers.
Power-Down Pin. This active low control pin puts the DAC into power-down mode.
Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
Eight Parallel Data Inputs.
POWER-ON
REGISTER
RESET
INPUT
Figure 5. AD5331 Functional Block Diagram
REGISTER
DAC
10-BIT
V
DAC
REF
3
Rev. A | Page 8 of 28
BUFFER
AD5331
V
POWER-DOWN
12
DD
LOGIC
PD
11
GND
5
4
V
OUT
Figure 6. AD5331 Pin Configuration
LDAC
V
GAIN
V
GND
REF
CLR
DB
DB
OUT
REF
WR
CS
8
9
or 0 V to 2 × V
10
2
3
4
5
6
7
8
9
1
(Not to Scale)
AD5331
TOP VIEW
10-BIT
REF
.
19
18
17
16
15
14
13
12
11
20
DB
DB
DB
DB
DB
DB
DB
DB
V
PD
DD
7
6
5
4
3
2
1
0