CS4364-CQZ Cirrus Logic Inc, CS4364-CQZ Datasheet
CS4364-CQZ
Specifications of CS4364-CQZ
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CS4364-CQZ Summary of contents
Page 1
... DSD conversion by di- rectly using the multi-element switched capacitor array. The CS4364 accepts PCM data at sample rates from 4 kHz to 216 kHz, DSD audio data, and delivers excel- lent sound quality. These features are ideal for multi- ...
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... Part Number ID (PART) [Read Only] ................................................................................... 33 6.1.2 Revision ID (REV) [Read Only] ............................................................................................ 33 6.2 Mode Control 1 (Address 02h) ...................................................................................................... 33 6.2.1 Control Port Enable (CPEN) ................................................................................................ 33 6.2.2 Freeze Controls (FREEZE) .................................................................................................. 33 6.2.3 PCM/DSD Selection (DSD/PCM)......................................................................................... 34 6.2.4 DAC Pair Disable (DACx_DIS) ............................................................................................ 34 6.2.5 Power Down (PDN).............................................................................................................. 34 2 .............................................................................................. 18 CS4364 DS619F1 ...
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... Volume Control (Address 0Bh, 0Ch, 0Eh, 0Fh, 11h, 12h)........................................................... 42 6.11.1 Digital Volume Control (xx_VOL7:0) .................................................................................. 42 6.12 PCM Clock Mode (Address 16h) ................................................................................................. 42 6.12.1 Master Clock Divide by 2 Enable (MCLKDIV).................................................................... 42 7. FILTER RESPONSE PLOTS ............................................................................................................... 43 8. REFERENCES...................................................................................................................................... 47 9. PARAMETER DEFINITIONS................................................................................................................ 47 10. PACKAGE DIMENSIONS .................................................................................................................. 48 11. ORDERING INFORMATION .............................................................................................................. 49 12. REVISION HISTORY ......................................................................................................................... 50 DS619F1 CS4364 3 ...
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... Figure 40. Quad-Speed (fast) Stopband Rejection .................................................................................... 45 Figure 41. Quad-Speed (fast) Transition Band .......................................................................................... 45 Figure 42. Quad-Speed (fast) Transition Band (detail) .............................................................................. 46 Figure 43. Quad-Speed (fast) Passband Ripple ........................................................................................ 46 Figure 44. Quad-Speed (slow) Stopband Rejection................................................................................... 46 Figure 45. Quad-Speed (slow) Transition Band......................................................................................... 46 Figure 46. Quad-Speed (slow) Transition Band (detail)............................................................................. 46 Figure 47. Quad-Speed (slow) Passband Ripple....................................................................................... 46 4 CS4364 DS619F1 ...
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... Table 4. PCM Digital Interface Format, Hardware Mode Options............................................................. 21 Table 5. Mode Selection, Hardware Mode Options .................................................................................. 21 Table 6. Direct Stream Digital (DSD), Hardware Mode Options ............................................................... 21 Table 7. Digital Interface Formats - PCM Mode........................................................................................ 35 Table 8. Digital Interface Formats - DSD Mode ........................................................................................ 35 Table 9. ATAPI Decode ............................................................................................................................ 41 Table 10. Example Digital Volume Settings .............................................................................................. 42 DS619F1 CS4364 5 ...
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... Refer to the Recommended Operating Conditions for appropriate voltages Quiescent Voltage (Output) - Filter connection for internal quiescent voltage DSD3 1 DSD2 2 DSD1 GND 5 6 MCLK CS4364 LRCK 7 SDIN1 8 SCLK 9 10 SDIN2 Pin Description CS4364 36 TST_OUT 35 AOUT3 AOUT4 34 TST_OUT GND 30 TST_OUT 29 AOUT5 28 AOUT6 27 TST_OUT 26 MUTE2 25 MUTE3 Table 1 illus- DS619F1 ...
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... Direct Stream Digital Input (Input) - Input for Direct Stream Digital serial audio data. DSD5, DSD6 47,46 DSD_SCLK 42 DSD Serial Clock (Input) - Serial clock for the Direct Stream Digital serial audio interface. DS619F1 Pin Description ® mode as shown in the Typical Connection Dia- CS4364 Tables 4 ™ mode. 7 ...
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... Digital internal power VD VLS Control port interface power VLC Any Pin Except Supplies I in Serial data port interface V IND-S Control port interface V IND stg CS4364 Min Typ Max 4.75 5.0 5.25 2.37 2.5 2.63 1.71 5.0 5.25 1.71 5.0 5.25 -40 - +85 ...
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... A-weighted (Note 2) unweighted 24-bit -0 dB THD+N -20 dB -60 dB 16-bit 0 dB - kHz) PCM, DSD processor V 64%•V FS Direct DSD Mode 47%•V Z OUT I OUTmax QMAX and includes attenuation due CS4364 C; Full-Scale 997 Hz ° Min Typ Max 97 103 - 94 100 - - -88 -82 - -80 -74 - -40 - ...
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... Valid with the recommended capacitor values on FILT+ and VQ as shown in 10 Symbol normal operation, VA VD= 2 Interface current, VLC VLS power-down state (all supplies 2.5 V normal operation (Note 6) power-down θ multi-layer JA θ dual-layer JA θ kHz) PSRR (60 Hz) CS4364 Min Typ Max Units - µ µ µA - 200 - - 360 400 ...
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... kHz - Fs = 44.1 kHz - kHz - to -0.01 dB corner corner kHz -0.01 .583 (Note 10 6.15/Fs to -0.01 dB corner corner kHz -0.01 .635 (Note 10 7.1/Fs “Filter Response Plots” on page CS4364 Typ Max Unit - .454 Fs - .499 Fs - +0. ±0. ±0. ±0. .430 Fs - .499 ...
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... Fs = 44.1 kHz - kHz - to -0.01 dB corner corner kHz -0.01 .792 (Note 10 5.4/Fs to -0.01 dB corner corner kHz -0.01 .868 (Note 10 6.6/Fs Min corner kHz -0. -0.1 dB corner corner 0 -0.1 CS4364 (Note 8) Typ Max Unit - 0.417 Fs - 0.499 Fs - +0. ±0. ±0. ±0. .296 Fs - .499 Fs - +0.01 ...
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... MUTEC Low-Level Output Voltage 13. Any pin except supplies. Transient currents ±100 mA on the input pins will not cause SCR latch-up DS619F1 Symbol (Note 13 Serial I Control I Serial I Control I Control I Control I/O = 1 max CS4364 Min Typ Max Units µ ± ...
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... MCLK frequencies. LRCK SCLK SDINx pF) L (Note 14) (Note 15) Single-Speed Mode Double-Speed Mode Quad-Speed Mode Single-Speed Mode Double-Speed Mode Quad-Speed Mode lcks sckh MSB Figure 1. Serial Audio Interface Timing CS4364 Symbol Min Max 1 - 1.024 55 108 s F 100 216 108 ...
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... Figure 3. Direct Stream Digital - Serial Audio Input Timing for Phase Modulation Mode DS619F1 = 30 pF) L Symbol Min 40 t 160 sclkl t 160 sclkh (64x Oversampled) 1.024 (128x Oversampled) 2.048 t 20 sdlrs t 20 sdh t -20 dpm t sclkh t sclkl t t sdlrs sdh t t dpm dpm CS4364 Typ Max Unit - 3.2 MHz - 6.4 MHz - - ...
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... high t t sud t sust hdd Figure 4. Control Port Timing - I²C Format CS4364 Min Max Unit - 100 kHz 500 - 4.7 - 4.0 - 4.7 - 4 250 - - 1 - 300 4.7 - 300 1000 , of SCL. fc Stop ...
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... L Symbol f sclk t srs (Note 17) t spi t csh t css t scl t sch t dsu (Note 18 (Note 19 (Note 19 css t scl t sch dsu t dh Figure 5. Control Port Timing - SPI Format CS4364 Min Max Unit - 6 MHz 500 - ns 500 - ns 1.0 - µ 100 ns - 100 all other times. ...
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... SDA/CDIN 17 ADO/CS CMOUT Note* 18 VLC 0.1 µF TST_OUT TST* GND GND *Pins: 10, 12, control port I operation 14, 44, 45 CS4364 + 0.1 µF 1 µF 39 Analog Conditioning and Muting Analog Conditioning 38 and Muting 35 Analog Conditioning and Muting 34 Analog Conditioning and Muting 29 Analog Conditioning and Muting 28 ...
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... AOUT6 MUTEC6 RST FILT+ CMOUT 18 VLC 0.1 µF TST_OUT GND TST* GND 5 31 *Pins: 14, 44, 45 CS4364 + 0.1 µF 1 µF 39 Analog Conditioning and Muting 41 38 Analog Conditioning and Muting 26 35 Analog Conditioning and Muting 25 34 Analog Conditioning and Muting 24 29 Analog Conditioning ...
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... SDINx, and the Serial Clock (SCLK) clocks audio data into the input data buffer. For more information on serial audio interfaces see AN282 “The 2-Channel Serial Audio Interface: A Tutorial”. The CS4364 can be configured in Hardware Mode by the M0, M1, M2, M3 and M4 pins and in Software Mode through I²C or SPI. ...
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... DSD data with a 2x MCLK to DSD data rate 128x oversampled DSD data with a 3x MCLK to DSD data rate 128x oversampled DSD data with a 4x MCLK to DSD data rate 128x oversampled DSD data with a 6x MCLK to DSD data rate CS4364 FORMAT FIGURE 0 ...
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... Figure 11. Format 3 - Right-Justified 24-bit Data 32 clocks LRCK Left Channel SCLK SDINx Figure 12. Format 4 - Right-Justified 20-bit Data 32 clocks LSB MSB + LSB MSB Figure 9. Format 1 - I² 24-bit Data CS4364 Figures 8-15. Data is Right Channel + LSB Right Channel + LSB Right Channel Right Channel Right Channel DS619F1 ...
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... The auto speed-mode detect feature allows for the automatic selection of speed mode based off of the in- coming sample rate. This allows the CS4364 to accept a wide range of sample rates with no external inter- vention necessary. The auto speed-mode detect feature is available in both Hardware and Software Mode. ...
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... Filter specifications can be found in 4.6 De-Emphasis The CS4364 includes on-chip digital de-emphasis filters. The de-emphasis feature is included to accommo- date older audio recordings that utilize pre-emphasis equalization as a means of noise reduction. shows the de-emphasis curve. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate the input sample rate does not match the coefficient which has been se- lected ...
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... CS4364, but may lower the sensitivity to board level routing of the DSD data signals. The CS4364 can detect errors in the DSD data which does not comply with the SACD specification. The STATIC_DSD and INVALID_DSD bits (Reg. 04h) allow the CS4364 to alter the incoming invalid DSD data. ...
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... The Typical Connection Diagram shows the rec- ommended power arrangements, with VA, VD, VLC, and VLS connected to clean supplies. If the ground planes are split between digital ground and analog ground, the GND pins of the CS4364 should be connect the analog ground plane. ...
Page 27
... The external mute circuitry needs to be self biased into an active state in order to be muted during reset. Upon release of reset, the CS4364 will detect the status of the MUTEC pins (high or low) and will then select that state as the polarity to drive when the mutes become active. The external-bias voltage level that the MUTEC pins see at the time of release of reset must meet the “ ...
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... Hardware sequence has begun advised that if the CPEN bit can not be set in time then the SDINx pins should remain static low (this way no audio data can be 28 Figure 21. Recommended Mute Circuitry Section 4.1. In this state, the registers are reset to the default CS4364 Section 4.1. In this state, the DS619F1 ...
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... There pin. Pin AD0 en- bus followed by the address byte. The upper 6 bits must be I²C 4.14.1) is set to 1, repeat the previous step until all the desired registers writes to other registers are desired necessary to initiate I²C CS4364 writes or reads and I²C 29 ...
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... Read section further reads from other registers are de- I² 1-8 Figure 22. Control Port Timing, I²C Mode 4.14.1) is set to 1, repeat the previous step until all the desired registers CS4364 read is the first operation performed on the I² 1-8 S top DS619F1 Write ...
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... INCR (Auto Map Increment Enable) Default = ‘0’ Disabled 1 - Enabled 4.15.2 MAP4-0 (Memory Address Pointer) Default = ‘00000’ DS619F1 0011000 byte ory A d dress P oin te r Figure 23. Control Port Timing, SPI Mode MAP4 MAP3 CS4364 LSB byte MAP2 MAP1 MAP0 ...
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... P2_DEM1 P2_DEM0 P2ATAPI4 P2ATAPI3 A2_VOL6 A2_VOL5 A2_VOL4 B2_VOL6 B2_VOL5 B2_VOL4 P3_DEM1 P3_DEM0 P3ATAPI4 P3ATAPI3 A3_VOL6 A3_VOL5 A3_VOL4 B3_VOL6 B3_VOL5 B3_VOL4 Reserved MCLKDIV Reserved CS4364 PART0 REV2 REV1 Reserved Reserved FM1 INVALID_D DSD_PM_ DSD_PM_ Reserved Reserved Reserved INV_B2 INV_A2 INV_B1 P2_A=B ...
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... PART4 PART3 PART2 0 1 6.1.1 Part Number ID (PART) [Read Only] 01100 - CS4364 6.1.2 Revision ID (REV) [Read Only] 000 - Revision A0 001 - Revision B0 Function: This read-only register can be used to identify the model and revision number of the device. 6.2 Mode Control 1 (Address 02h) ...
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... The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in Note: While in PCM Mode, the DIF bits should only be changed when the power-down (PDN) bit is set to ensure proper switching from one mode to another DIF0 Reserved Figures 8-15. CS4364 Reserved FM1 FM0 DS619F1 ...
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... DSD data with a 2x MCLK to DSD data rate. 1 128x oversampled DSD data with a 3x MCLK to DSD data rate. 0 128x oversampled DSD data with a 4x MCLK to DSD data rate. 1 128x oversampled DSD data with a 6x MCLK to DSD data rate. Table 8. Digital Interface Formats - DSD Mode CS4364 Format FIGURE ...
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... DSD Phase Modulation Mode Enable (DSD_PM_EN) Function: When set to 1, DSD Phase Modulation Input Mode is enabled and the DSD_PM_MODE bit should be set accordingly. When set to 0 (default), this function is disabled (DSD normal mode). 36 24.) CS4364 Section 2), the dynamic range DS619F1 ...
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... AOUT1A and AOUT1B on MUTEC1, AOUT2A and AOUT2B on MUTEC2, and AOUT3A and AOUT3B on MUTEC3. 6.7.2 Channel A Volume = Channel B Volume (Px_A=B) Default = Disabled 1 - Enabled DS619F1 Reserved Reserved INV_A3 INV_B2 P1_A=B P2_A CS4364 Reserved Reserved FILT_SEL INV_A2 INV_B1 INV_A1 P3_A=B Reserved SNGLVOL ...
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... Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a time-out period between 512 and 1024 sample periods (10 21 kHz RMP_DN PAMUTE CS4364 DAMUTE MUTE_P1 MUTE_P0 DS619F1 ...
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... A single bit not fitting the repeated mute pattern (mentioned above) will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained and the Mute Control pin will go active during the mute period. DS619F1 CS4364 39 ...
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... The MUTE pins will go active during the mute period according to the MUTEC bits. 6.10 Mixing Control (Address 0Ah, 0Dh, 10h, 13h Reserved Px_DEM1 Px_DEM0 0 0 6.10.1 De-Emphasis Control (PX_DEM1:0) Default = Disabled 01 - 44.1 kHz kHz kHz Function: 40 for the description MUTE_A3 MUTE_B2 PxATAPI4 PxATAPI3 CS4364 MUTE_A2 MUTE_B1 MUTE_A1 PxATAPI2 PxATAPI1 PxATAPI0 DS619F1 ...
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... De-emphasis is only available in Single-Speed Mode. 6.10.2 ATAPI Channel Mixing and Muting (ATAPI) Default = 01001 - AOUTAx=aL, AOUTBx=bR (Stereo) Function: The CS4364 implements the channel mixing functions of the ATAPI CD-ROM specification. The ATAPI functions are applied per A-B pair. Refer to ATAPI4 ATAPI3 ATAPI2 ...
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... Table 10 are approximate. The actual attenuation is determined Decimal Value 00000000 0 00000001 1 00000110 6 11111111 255 Table 10. Example Digital Volume Settings Reserved Reserved CS4364 xx_VOL2 xx_VOL1 xx_VOL0 Table 10. The volume changes are imple- Volume Setting 0 dB -0.5 dB -3.0 dB -127 Reserved Reserved Reserved ...
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... Figure 27. Single-Speed (fast) Passband Ripple 0 −20 −40 −60 −80 −100 −120 0.8 0.9 1 0.4 0.42 Figure 29. Single-Speed (slow) Transition Band CS4364 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 Frequency(normalized to Fs) 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency(normalized to Fs) 0 ...
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... Figure 33. Double-Speed (fast) Transition Band 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 0.52 0.53 0.54 0.55 0 0.05 Figure 35. Double-Speed (fast) Passband Ripple CS4364 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency(normalized to Fs) 0.44 0.46 0.48 0.5 0.52 0.54 0.56 ...
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... Figure 39. Double-Speed (slow) Passband Ripple 100 120 0.2 0.7 0.8 0.9 1 Figure 41. Quad-Speed (fast) Transition Band CS4364 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0.05 0.1 0.15 0.2 0.25 0.3 Frequency(normalized to Fs) 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0 ...
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... Figure 45. Quad-Speed (slow) Transition Band 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 0 0.02 0.52 0.53 0.54 0.55 Figure 47. Quad-Speed (slow) Passband Ripple CS4364 0.05 0.1 0.15 0.2 0.25 Frequency(normalized to Fs) 0.3 0.4 0.5 0.6 0.7 0.8 Frequency(normalized to Fs) 0.04 0.06 0.08 ...
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... Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. DS619F1 CS4364 47 ...
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... Nominal pin pitch is 0.50 mm Controlling dimension is mm. JEDEC Designation: MS022 CS4364 A A1 MILLIMETERS MIN NOM MAX --- 1.40 1.60 0.05 0.10 0.15 0.17 0.22 0.27 8.70 9.0 BSC 9 ...
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... INFORMATION Product Description 114 dB, 192 kHz 6- CS4364 channel D/A Converter CDB4364 CS4364 Evaluation Board DS619F1 Package Pb-Free Grade Temp Range 48-pin YES Commercial -40° to +85° C LQFP - - CS4364 Container Order # Tray CS4364-CQZ Tape & Reel CS4364-CQZR - - CDB4364 49 ...
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... Direct Stream Digital is a registered trademark of Sony Kabushiki Kaisha TA Sony Corporation. DSD is a trademark of Sony Kabushiki Kaisha TA Sony Corporation. 50 Changes “DAC Pair Disable (DACx_DIS)” on page 34 “Digital Interface Format (DIF)” on page 34 “Mode Select” on page 21 “DAC Analog Characteristics” on page 9 Power and Thermal Characteristics “IMPORTANT NOTICE” on page 50 CS4364 DS619F1 ...